{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T13:00:25Z","timestamp":1725541225736},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/vldi-dat.2013.6533867","type":"proceedings-article","created":{"date-parts":[[2013,6,26]],"date-time":"2013-06-26T13:24:15Z","timestamp":1372253055000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3"],"prefix":"10.1109","author":[{"given":"R.","family":"Hori","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Ueoka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Otani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Yoshikawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Fujino","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"EASIC Corporation-Low Cost FPGA & Low Power FPGA & Low NRE ASIC with High Speed Transceivers","year":"0","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"journal-title":"Analysis Photomask Business Model Is Broken","year":"0","author":"ladepus","key":"1"},{"key":"10","first-page":"21","article-title":"Viaprogrammable logic array VPEX2 with configurable DFF using 2 logic elements","author":"fujino","year":"2009","journal-title":"Proc on Intl Symposium on Integrated Circuits (ISIC"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E95.A.1518"},{"year":"0","key":"6"},{"journal-title":"Faraday Structured ASIC Technology","year":"0","key":"5"},{"journal-title":"FPGA CPLD and ASIC from Altera","year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e91-c.4.509"},{"key":"8","first-page":"17","article-title":"Via-configurable logic block architectures for standard cell like structured ASICs","author":"tung","year":"2009","journal-title":"Proc on Intl Symposium on Integrated Circuits (ISIC"},{"key":"11","first-page":"470","article-title":"The development of CAD system for via programmable structured ASIC VPEX3","author":"hori","year":"2012","journal-title":"The Workshop on Synthesis And System Integration of Mixed Information technologies"}],"event":{"name":"2013 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2013,4,22]]},"location":"Hsinchu","end":{"date-parts":[[2013,4,24]]}},"container-title":["2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6526674\/6533796\/06533867.pdf?arnumber=6533867","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T14:50:49Z","timestamp":1490194249000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6533867\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/vldi-dat.2013.6533867","relation":{},"subject":[],"published":{"date-parts":[[2013,4]]}}}