{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T15:56:12Z","timestamp":1725810972014},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/vlsi-dat.2012.6212590","type":"proceedings-article","created":{"date-parts":[[2012,6,19]],"date-time":"2012-06-19T17:01:09Z","timestamp":1340125269000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["A slew rate self-adjusting 2×VDD output buffer With PVT compensation"],"prefix":"10.1109","author":[{"family":"Chih-Lin Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hsin-Yuan Tseng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Ron-Chi Kuo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chua-Chin Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810030"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373467"},{"key":"1","first-page":"599","article-title":"Short-channel effects and device models","author":"razavi","year":"2001","journal-title":"Design of Analog CMOS Integrated Circuits McGraw-Hill"},{"key":"7","first-page":"293","article-title":"A highspeed memory interface circuit tolerant to PVT variations and channel noise","author":"park","year":"2001","journal-title":"Proc European Solid-State Circuits Conf"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ASQED.2009.5206272"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2008.4675036"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.813253"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2050941"}],"event":{"name":"2012 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2012,4,23]]},"location":"Hsinchu","end":{"date-parts":[[2012,4,25]]}},"container-title":["Proceedings of Technical Program of 2012 VLSI Design, Automation and Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6204369\/6212573\/06212590.pdf?arnumber=6212590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T12:37:38Z","timestamp":1490099858000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6212590\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat.2012.6212590","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}