{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:49:53Z","timestamp":1725490193785},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/vlsi-dat.2012.6212619","type":"proceedings-article","created":{"date-parts":[[2012,6,19]],"date-time":"2012-06-19T17:01:09Z","timestamp":1340125269000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["An efficient memory controller for 3D heterogeneous integration platform"],"prefix":"10.1109","author":[{"family":"Yi-Jun Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chih-Chyau Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Shih-Lun Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chun-Chieh Chiu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chun-Chieh Chu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chien-Ming Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chun-Ming Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2009.2022075"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1047744"},{"journal-title":"PrimeCell AHB DDR and Nand Memory Controller (PL244) Technical Reference Manual","year":"0","key":"10"},{"key":"1","article-title":"Surviving the SoC Revolution: A guide to platformbased designs","author":"chang","year":"1999","journal-title":"Kluwer Academic Norwell Mass"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2011.5783593"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2006.283867"},{"key":"5","article-title":"A Case Study of the novel low-cost soc silicon prototyping service for taiwan academia","author":"lee","year":"2007","journal-title":"Innovations"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4542184"},{"journal-title":"PrimeCell AHB SDR and SRAM\/NOR Memory Controller (PL243) Technical Reference Manual","year":"0","key":"9"},{"year":"0","key":"8"}],"event":{"name":"2012 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2012,4,23]]},"location":"Hsinchu","end":{"date-parts":[[2012,4,25]]}},"container-title":["Proceedings of Technical Program of 2012 VLSI Design, Automation and Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6204369\/6212573\/06212619.pdf?arnumber=6212619","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T12:57:49Z","timestamp":1490101069000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6212619\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat.2012.6212619","relation":{},"subject":[],"published":{"date-parts":[[2012,4]]}}}