{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T16:42:07Z","timestamp":1725468127521},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/vlsi-dat.2015.7114514","type":"proceedings-article","created":{"date-parts":[[2015,6,3]],"date-time":"2015-06-03T19:28:25Z","timestamp":1433359705000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction"],"prefix":"10.1109","author":[{"given":"Yi-Ping","family":"Kuo","sequence":"first","affiliation":[]},{"given":"Po-Tsang","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Chung-Shiang","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Yu-Jie","family":"Liang","sequence":"additional","affiliation":[]},{"given":"Ching-Te","family":"Chuang","sequence":"additional","affiliation":[]},{"given":"Yuan-Hua","family":"Chu","sequence":"additional","affiliation":[]},{"given":"Wei","family":"Hwang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2143438"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2012.0114"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2014.6948914"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185354"},{"key":"ref2","first-page":"1","article-title":"0.5-V input digital LDO with 98.7% current efficiency and 2.7-uA quiescent current in 65nm CMOS","author":"okuma","year":"2010","journal-title":"IEEE Custom Integrated Circuits Conf (CICC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885060"}],"event":{"name":"2015 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2015,4,27]]},"location":"Hsinchu, Taiwan","end":{"date-parts":[[2015,4,29]]}},"container-title":["VLSI Design, Automation and Test(VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7111694\/7114493\/07114514.pdf?arnumber=7114514","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T19:11:04Z","timestamp":1490382664000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7114514\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat.2015.7114514","relation":{},"subject":[],"published":{"date-parts":[[2015,4]]}}}