{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T11:02:15Z","timestamp":1725534135864},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/vlsi-dat.2015.7114578","type":"proceedings-article","created":{"date-parts":[[2015,6,3]],"date-time":"2015-06-03T15:28:25Z","timestamp":1433345305000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Adaptive granularity and coordinated management for timely prefetching in multi-core systems"],"prefix":"10.1109","author":[{"given":"Chia-Jung","family":"Chang","sequence":"first","affiliation":[]},{"given":"Yin-Chi","family":"Peng","sequence":"additional","affiliation":[]},{"given":"Chien-Chih","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Tien-Fu","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Pen-Chung","family":"Yew","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669154"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2007.17"},{"key":"ref6","article-title":"POWER4 system microarchitecture","author":"tendler","year":"2001","journal-title":"IBM Technical White Paper"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CIS.2011.68"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1810085.1810110"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2133382.2133384"},{"key":"ref2","article-title":"Inside Intel&#x00AE; core&#x2122; microarchitecture and smart memory access","author":"doweck","year":"2006","journal-title":"Intel Corporation"},{"key":"ref9","article-title":"Cross-layer dynamic prefetching allocation strategies for high-performance multicores","author":"peng","year":"2013","journal-title":"VLSI-DAT"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/12.381947"}],"event":{"name":"2015 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2015,4,27]]},"location":"Hsinchu, Taiwan","end":{"date-parts":[[2015,4,29]]}},"container-title":["VLSI Design, Automation and Test(VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7111694\/7114493\/07114578.pdf?arnumber=7114578","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T15:04:03Z","timestamp":1490367843000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7114578\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat.2015.7114578","relation":{},"subject":[],"published":{"date-parts":[[2015,4]]}}}