{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T11:53:17Z","timestamp":1761997997938,"version":"build-2065373602"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/vlsi-dat.2017.7939641","type":"proceedings-article","created":{"date-parts":[[2017,6,8]],"date-time":"2017-06-08T16:42:47Z","timestamp":1496940167000},"page":"1-4","source":"Crossref","is-referenced-by-count":4,"title":["Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine"],"prefix":"10.1109","author":[{"given":"Chia-Heng","family":"Wu","sequence":"first","affiliation":[]},{"given":"Ting-Sheng","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ding-Yuan","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Tsung-Te","family":"Liu","sequence":"additional","affiliation":[]},{"given":"An-Yeu","family":"Wu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2012.6402898"},{"key":"ref3","first-page":"129","article-title":"Parsing natural scenes and natural language with recursive neural networks","author":"socher","year":"2011","journal-title":"Proc International Conference on Machine Learning (ICML)"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"661","DOI":"10.1109\/TNNLS.2015.2434847","article-title":"Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology","volume":"27","author":"tala?ka","year":"2016","journal-title":"IEEE Trans on Neural Networks and Learning Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2013.6674636"},{"key":"ref8","first-page":"iv-209","article-title":"A scalable sorting architecture based on maskalbe WTA\/MAX circuit","volume":"4","author":"ou","year":"2002","journal-title":"Proc Int Symp Circuits and Systems (ISCAS)"},{"key":"ref7","article-title":"High-Speed Tree-based 64-Bit Binary Comparator using New Approach","volume":"61","author":"anand","year":"2013","journal-title":"International Journal of Computer Applications"},{"key":"ref2","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Advances in Neural Information Processing Systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810787"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2014.09.003"}],"event":{"name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2017,4,24]]},"location":"Hsinchu, Taiwan","end":{"date-parts":[[2017,4,27]]}},"container-title":["2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7936426\/7939640\/07939641.pdf?arnumber=7939641","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,25]],"date-time":"2019-09-25T16:00:35Z","timestamp":1569427235000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7939641\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat.2017.7939641","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}