{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T17:35:54Z","timestamp":1725557754164},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/vlsi-dat.2017.7939659","type":"proceedings-article","created":{"date-parts":[[2017,6,8]],"date-time":"2017-06-08T16:42:47Z","timestamp":1496940167000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["An analytical placer for heterogeneous FPGAs via rough-placed packing"],"prefix":"10.1109","author":[{"given":"Wan-Ning","family":"Wu","sequence":"first","affiliation":[]},{"given":"Chen","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ching-Yu","family":"Chin","sequence":"additional","affiliation":[]},{"given":"Chun-Kai","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Hung-Ming","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001421"},{"journal-title":"ISPD 2016 routability-driven FPGA placement contest","year":"2016","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2170567"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055179"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717776"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.925783"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353640"},{"key":"ref17","first-page":"48","article-title":"An efficient and effective detailed placement algorithm","author":"pan","year":"2005","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950457"},{"key":"ref4","first-page":"4","article-title":"Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation","author":"marrakchi","year":"2005","journal-title":"International Conference on Reconfigurable Computing and FPGAs"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024908"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380635"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412103"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842812"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","article-title":"VPR: A new packing, placement and routing tool for FPGA research","author":"betz","year":"1997","journal-title":"International Workshop on Field-Programmable Logic and Applications"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370567"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339278"}],"event":{"name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2017,4,24]]},"location":"Hsinchu, Taiwan","end":{"date-parts":[[2017,4,27]]}},"container-title":["2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7936426\/7939640\/07939659.pdf?arnumber=7939659","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,25]],"date-time":"2019-09-25T16:00:20Z","timestamp":1569427220000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7939659\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat.2017.7939659","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}