{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:16:47Z","timestamp":1729660607677,"version":"3.28.0"},"reference-count":50,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/vlsi-dat.2017.7939702","type":"proceedings-article","created":{"date-parts":[[2017,6,8]],"date-time":"2017-06-08T16:42:47Z","timestamp":1496940167000},"page":"1-3","source":"Crossref","is-referenced-by-count":0,"title":["Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs"],"prefix":"10.1109","author":[{"given":"Tetsuo","family":"Endoh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.54.04DM06"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.54.04DE03"},{"key":"ref33","article-title":"STT-MRAM Technology and Its NV-Logic Applications for Ultimate Power","author":"endoh","year":"2014","journal-title":"CMOS Emerging Technologies Research MINATEC"},{"key":"ref32","article-title":"A-High frequency Level-up shifter Based on 0.18um Vertical MOSFETs with More than 70% Reduction of Overshoot-voltage Above VDD","author":"tanoi","year":"2014","journal-title":"International Conference on Solid State Devices and Materials (SSDM)"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.7567\/SSDM.2014.A-8-2"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.7567\/SSDM.2014.A-7-1"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.54.04DD05"},{"key":"ref36","article-title":"Future Memory Technology with Vertical MOSFET and STT-MRAM for Ultra Low Power Systems","author":"endoh","year":"2015","journal-title":"KCS (Korean Conference on Semiconductors)"},{"key":"ref35","article-title":"STT-MRAM, NV-logic with MTJ and high density memory with Vertical MOSFET","author":"endoh","year":"2014","journal-title":"SEMATECH Beyond CMOS Workshop Materials & Technologies for Beyond CMOS"},{"key":"ref34","article-title":"The dynamic interaction effect due to oscillatory stray field from programing cell in 10nm design p-MTJ array","author":"ohuchida","year":"2014","journal-title":"59th Annu Conf Magn Magn Mater"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.7567\/SSDM.2014.J-7-1"},{"key":"ref27","article-title":"Spintronics Based NV-Memory\/Logic for High Performance & Low Power","author":"endoh","year":"2013","journal-title":"2013 VLSI Technology Short Course of 2013 Symposium on VLSI"},{"key":"ref29","article-title":"A 500ps\/8.5ns Array Read\/Write Latency 1Mb Twin 1T1MTJ STTMRAM designed in 90nm CMOS\/40nm MTJ Process with Novel Positive Feedback S\/A Circuit","author":"ohsawa","year":"2014","journal-title":"International Conference on Solid State Devices and Materials (SSDM)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.753680"},{"key":"ref1","first-page":"1491","article-title":"The Analysis of the Stacked-Surrounding Gate Transistor (S-SGT) DRAM for the High Speed and Low Voltage Operation","volume":"e81 c","author":"endoh","year":"1998","journal-title":"IEICE Trans on Elec"},{"key":"ref20","article-title":"MTJ based Non Volatile Logic for Ultimate Power Management","author":"endoh","year":"2012","journal-title":"The 19th ICM2012 with SCES"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.51.02BD01"},{"key":"ref21","article-title":"MTJ based nonvolatile SRAM and low power nonvolatile logic-in-memory architecture","author":"endoh","year":"2012","journal-title":"Intermag 2012"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.51.02BE07"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.51.02BM02"},{"key":"ref26","article-title":"1.5nsec\/2.1nsec Random Read\/Write Cycle 1Mb STT-RAM Using 6T2MTJ Cell with Background Write for Nonvolatile e-Memories","author":"ohsawa","year":"2013","journal-title":"2013 Symposium on VLSI Circuits Digest"},{"key":"ref25","article-title":"Low-Current Domain Wall Motion MRAM with Perpendicularly Magnetized CoFeB\/MgO Magnetic Tunnel Junction and Underlying Hard Magnets","author":"suzuki","year":"2013","journal-title":"2013 Symposium on VLSI Technology Digest"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547704"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.7567\/SSDM.2011.F-1-2"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243782"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.54.04DE08"},{"key":"ref12","first-page":"110c","article-title":"A 1.5nsec\/2.1nsec random read\/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories","author":"ohsawa","year":"2013","journal-title":"2013 Symposium on VLSI Circuits VLSIC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131487"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E94.C.760"},{"key":"ref15","article-title":"Restructuring of Memory Hierarchy in System and No-Standby-Power Nonvolatile Logic with STT-MRAM Technology","author":"endoh","year":"2012","journal-title":"14th Leti Annual Review A"},{"key":"ref16","first-page":"46","article-title":"1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique with l.0ns\/200ps Wake-up\/Power-off Times","author":"ohsawa","year":"2012","journal-title":"Symposia on VLSI Technology and Circuits"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242475"},{"key":"ref18","article-title":"Restructuring of Memory Hierarchy in System and No-Standby-Power Nonvolatile Logic with STT-MRAM Technology","author":"endoh","year":"2012","journal-title":"IMEC Seminar 2012"},{"key":"ref19","article-title":"MTJ Based Non-volatile RAM and Low Power Nonvolatile Logic Suitable to Pipeline Architecture","author":"endoh","year":"2012","journal-title":"The 8th Annual SEMATECH Symposium Japan 2012"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2001.979396"},{"key":"ref3","first-page":"447","article-title":"New Three Dimensional (3D) Memory Array Architecture For Future Ultra High Density DRAM","volume":"2","author":"endoh","year":"2000","journal-title":"Proc 22nd International Conference in Microelectronics"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E94.C.686"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.809429"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E93.C.557"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E92.C.598"},{"key":"ref49","article-title":"Demonstration of yield improvement for on-via MTJ using a 2-Mbit 1T-lMTJ STT-MRAM test chip","author":"koike","year":"2016","journal-title":"8th International Memory Workshop"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.7567\/SSDM.2011.F-1-3"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2016.2518203"},{"key":"ref45","doi-asserted-by":"crossref","DOI":"10.7567\/SSDM.2016.G-3-04","article-title":"New Model of Switching Delay Induced by Modulation Effect of Damping and STT Pumping Balance With Programing Current and Interference Phenomena in P-MTJ Array","author":"ohuchida","year":"2016","journal-title":"International Conference on Solid State Devices and Materials (SSDM) 2016"},{"key":"ref48","article-title":"Effect of MTJ Resistance Fluctuations on Synapse Stability of MTJ-Based Nonvolatile Neuron Circuit for High-Speed Object Recognition","author":"ma","year":"2016","journal-title":"2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices"},{"key":"ref47","doi-asserted-by":"crossref","DOI":"10.7567\/SSDM.2016.B-2-06","article-title":"A Compact and Ultra-Low-Power STT-MRAM-Based Associative Memory for Nearest Neighbor Search with Full Adaptivity of Template Data Format Employing Current-Mode Similarity Evaluation and Time-Domain Minimum Searching","author":"ma","year":"2016","journal-title":"International Conference on Solid State Devices and Materials (SSDM) 2016"},{"key":"ref42","article-title":"High Performance STT-MRAM and 3D NAND Memory with Spintronics and Vertical MOSFET Technology","author":"endoh","year":"2016","journal-title":"SEMICON WEST 2016"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.54.04DC11"},{"key":"ref44","article-title":"A $600\\!-\\!\\mu\\text{W}$ ultra-low-power associative processor based on MTJ nonvolatile memories with autonomic intelligent power-gating scheme","author":"ma","year":"2016","journal-title":"The 2nd ImPACT International Symposium on Spintronic Memory Circuit and Storage"},{"key":"ref43","article-title":"STT-MRAM and MTJ\/CMOS Hybrid NV-logic for Low Power Systems","author":"endoh","year":"2016","journal-title":"EMN Las Vegas Meetings"}],"event":{"name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2017,4,24]]},"location":"Hsinchu, Taiwan","end":{"date-parts":[[2017,4,27]]}},"container-title":["2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7936426\/7939640\/07939702.pdf?arnumber=7939702","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,25]],"date-time":"2019-09-25T16:00:34Z","timestamp":1569427234000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7939702\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":50,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat.2017.7939702","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}