{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T10:43:55Z","timestamp":1762253035133},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/vlsi-dat.2019.8741773","type":"proceedings-article","created":{"date-parts":[[2019,6,21]],"date-time":"2019-06-21T02:19:04Z","timestamp":1561083544000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model"],"prefix":"10.1109","author":[{"given":"Chao-Jun","family":"Shang","sequence":"first","affiliation":[]},{"given":"Cheng-Hung","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Kuen-Jong","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Yu-Hsiang","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2266374"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.59"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783759"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.32"},{"key":"ref8","article-title":"Identifying high timing variability speed-limiting paths under aging","author":"srivastava","year":"2017","journal-title":"Proc of IEEE Latin-American Test Symposium"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2017.8242072"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.28"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.120"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261012"}],"event":{"name":"2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2019,4,22]]},"location":"Hsinchu, Taiwan","end":{"date-parts":[[2019,4,25]]}},"container-title":["2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8734473\/8741402\/08741773.pdf?arnumber=8741773","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:07:20Z","timestamp":1657854440000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8741773\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat.2019.8741773","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}