{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,22]],"date-time":"2025-11-22T11:22:19Z","timestamp":1763810539055},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,4,19]],"date-time":"2021-04-19T00:00:00Z","timestamp":1618790400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,19]],"date-time":"2021-04-19T00:00:00Z","timestamp":1618790400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,19]],"date-time":"2021-04-19T00:00:00Z","timestamp":1618790400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,4,19]]},"DOI":"10.1109\/vlsi-dat52063.2021.9427349","type":"proceedings-article","created":{"date-parts":[[2021,5,12]],"date-time":"2021-05-12T20:07:35Z","timestamp":1620850055000},"page":"1-2","source":"Crossref","is-referenced-by-count":7,"title":["A Reconfigurable In-SRAM Computing Architecture for DCNN Applications"],"prefix":"10.1109","author":[{"given":"Yu-Hsien","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chi","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chia-Lin","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kang-Yu","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jia-Yin","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shyh-Jye","family":"Jou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2019.8916327"},{"article-title":"A 481pJ\/decision 3.4M decision\/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array","year":"2016","author":"kang","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s13244-018-0639-9"}],"event":{"name":"2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2021,4,19]]},"location":"Hsinchu, Taiwan","end":{"date-parts":[[2021,4,22]]}},"container-title":["2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9427295\/9427308\/09427349.pdf?arnumber=9427349","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:41:22Z","timestamp":1652197282000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9427349\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,19]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/vlsi-dat52063.2021.9427349","relation":{},"subject":[],"published":{"date-parts":[[2021,4,19]]}}}