{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,2]],"date-time":"2025-08-02T04:31:36Z","timestamp":1754109096808},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,10]]},"DOI":"10.1109\/vlsi-soc.2012.6379003","type":"proceedings-article","created":{"date-parts":[[2012,12,18]],"date-time":"2012-12-18T21:55:47Z","timestamp":1355867747000},"page":"41-45","source":"Crossref","is-referenced-by-count":11,"title":["CMOS implementation of static threshold gates with hysteresis: A new approach"],"prefix":"10.1109","author":[{"given":"Farhad A.","family":"Parsan","sequence":"first","affiliation":[]},{"given":"Scott C.","family":"Smith","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2000.836983"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.2200\/S00202ED1V01Y200907DCS023"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1007\/BF01788562"},{"key":"1","first-page":"66","article-title":"Measuring an asynchronous processor's power and noise","author":"mccardle","year":"0","journal-title":"Proc Synopsys Users Group Conf (SNUG) 2001"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2012.6292040"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548905"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/92.736128"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.706841"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(92)90001-F"},{"key":"8","first-page":"218","article-title":"System timing","author":"seitz","year":"1980","journal-title":"Introduction to VLSI Systems"},{"journal-title":"Asynchronous Logics and Application to Information Processing","year":"1963","author":"muller","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(01)00013-X"}],"event":{"name":"2012 IEEE\/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)","start":{"date-parts":[[2012,10,7]]},"location":"Santa Cruz, CA, USA","end":{"date-parts":[[2012,10,10]]}},"container-title":["2012 IEEE\/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)"],"original-title":[],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T15:25:47Z","timestamp":1602689147000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6379003"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2012.6379003","relation":{},"subject":[],"published":{"date-parts":[[2012,10]]}}}