{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T08:38:37Z","timestamp":1725439117293},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,10]]},"DOI":"10.1109\/vlsi-soc.2012.6379034","type":"proceedings-article","created":{"date-parts":[[2012,12,18]],"date-time":"2012-12-18T16:55:47Z","timestamp":1355849747000},"page":"225-230","source":"Crossref","is-referenced-by-count":0,"title":["Evaluation of fault tolerant technique based on homogeneous FPGA architecture"],"prefix":"10.1109","author":[{"given":"Yuki","family":"Nishitani","sequence":"first","affiliation":[]},{"given":"Kazuki","family":"Inoue","sequence":"additional","affiliation":[]},{"given":"Motoki","family":"Amagasaki","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Iida","sequence":"additional","affiliation":[]},{"given":"Morihiro","family":"Kuga","sequence":"additional","affiliation":[]},{"given":"Toshinori","family":"Sueyoshi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.E95.D.303"},{"journal-title":"\"ABC A System for Sequential Synthesis and Verification \" [Online]","year":"0","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.59"},{"key":"7","doi-asserted-by":"crossref","first-page":"187","DOI":"10.1145\/329166.329205","article-title":"Tolerating operational faults in cluster-based fpgas","author":"lakamraju","year":"0","journal-title":"Proceedings of the ACMISIGDA International Symposium on Field Programmable Gate Arrays 2000"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/92.273147"},{"key":"5","article-title":"Fpga with self-repair capabilities","author":"durand","year":"0","journal-title":"ACM Int'l Workshop on FPGAs 1994"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1142155.1142167"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"8","first-page":"122","article-title":"Analytical framework for switch block design","author":"lemieux","year":"0","journal-title":"Proceedings of International Conference on Field-Programmable Logic and Applications(FPL) 2002"}],"event":{"name":"2012 IEEE\/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)","start":{"date-parts":[[2012,10,7]]},"location":"Santa Cruz, CA, USA","end":{"date-parts":[[2012,10,10]]}},"container-title":["2012 IEEE\/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)"],"original-title":[],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T11:25:52Z","timestamp":1602674752000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6379034"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,10]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2012.6379034","relation":{},"subject":[],"published":{"date-parts":[[2012,10]]}}}