{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T06:23:41Z","timestamp":1725431021924},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/vlsi-soc.2013.6673241","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T19:45:44Z","timestamp":1386186344000},"page":"33-38","source":"Crossref","is-referenced-by-count":1,"title":["On the design of modulo 2&lt;sup&gt;n&lt;\/sup&gt;&amp;#x00B1;1 residue generators"],"prefix":"10.1109","author":[{"given":"Kostas","family":"Tsoumanis","sequence":"first","affiliation":[]},{"given":"Constantinos","family":"Efstathiou","sequence":"additional","affiliation":[]},{"given":"Nikos","family":"Moschopoulos","sequence":"additional","affiliation":[]},{"given":"Kiamal","family":"Pekmestzi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","article-title":"Hardware implementation of residue generators with respect to 2A+1 Moduli","author":"toyoshima","year":"1997","journal-title":"Proc of 7th Int Symposium on IC Technology Systems &Applications (ISIC)"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.49"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/12.250610"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5117780"},{"key":"16","first-page":"295","article-title":"Area-time efficient multi-moduli adder design","author":"vergos","year":"2010","journal-title":"Proc of XXV Conference on Design of Circuits and Integrated Systems (DCIS)"},{"key":"13","doi-asserted-by":"crossref","first-page":"1630","DOI":"10.1109\/ISCAS.2005.1464916","article-title":"A configurable dual moduli multi-operand modulo adder","author":"chang","year":"2005","journal-title":"Proc IEEE Int Symp Circuits and Systems"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2006.342349"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2005.858612"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060059"},{"key":"21","article-title":"On the design of configurable modulo 2n1 residue generators","author":"efstathiou","year":"2012","journal-title":"Proc Euromicro Conf Digital System Design (DSD)"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2009.04.002"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:19941391"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/78.747787"},{"journal-title":"Binary Adder Architectures for Cell-Based VLSI and Their Synthesis","year":"1998","author":"zimmermann","key":"24"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1960.5219822"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378155"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2003.1231911"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1976.1162834"},{"key":"1","doi-asserted-by":"crossref","DOI":"10.1142\/p523","author":"omondi","year":"2007","journal-title":"Residue Number Systems Theory and Implementation"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.2"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1016\/S0045-7906(97)00033-5"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1049\/el:20030084"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-005-1186-4"},{"key":"9","article-title":"Residue arithmetic for variation-tolerant design of multiply-Add units","author":"kouretas","year":"2009","journal-title":"Proc of Int Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS)"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MELCON.2006.1653327"}],"event":{"name":"2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2013,10,7]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6662534\/6673221\/06673241.pdf?arnumber=6673241","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,4]],"date-time":"2019-08-04T12:18:15Z","timestamp":1564921095000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6673241\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2013.6673241","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}