{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:42:09Z","timestamp":1730302929037,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/vlsi-soc.2013.6673261","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T19:45:44Z","timestamp":1386186344000},"page":"118-123","source":"Crossref","is-referenced-by-count":2,"title":["A basic-block power annotation approach for fast and accurate embedded software power estimation"],"prefix":"10.1109","author":[{"given":"Chien-Min","family":"Lee","sequence":"first","affiliation":[]},{"given":"Chi-Kang","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ren-Song","family":"Tsay","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629475"},{"key":"17","first-page":"55","article-title":"Automatic synthesis of highspeed processor simulators","author":"burtscher","year":"2004","journal-title":"Proc of MICRO"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSS.2000.874044"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391552"},{"journal-title":"OR1200 OpenRISC Processor","year":"0","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1450135.1450194"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370363"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337436"},{"key":"12","article-title":"The XTREM power and performance simulator for the intel Xscale core: Design and experiences","volume":"6","author":"contreras","year":"2007","journal-title":"ACM Trans Embedded Comput Syst (TECS)"},{"key":"21","first-page":"341","article-title":"Cycle-count-Accurate processor modeling for fast and accurate system-level Simulation","author":"lo","year":"2011","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE)"},{"year":"0","key":"3"},{"journal-title":"Synopsys HSPICE","year":"0","key":"20"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-1453-0_9"},{"journal-title":"Electronic Design Automation for Integrated Circuits Handbook","year":"2006","author":"lavagno","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347378"},{"journal-title":"Synopsys Design Compiler PrimePower","year":"0","key":"7"},{"key":"6","first-page":"525","article-title":"An MPSoC performance estimation framework using transaction level modeling","author":"atitallah","year":"2007","journal-title":"Proc RTCSA"},{"key":"5","first-page":"235","article-title":"Source-level timing annotation for fast and accurate TLM computation model Generation","author":"lin","year":"2010","journal-title":"Proc of ASPDAC"},{"key":"4","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/334012.334019"},{"key":"8","first-page":"123","article-title":"Power analysis and minimization techniques for embedded DSP software","author":"lee","year":"1997","journal-title":"IEEE Trans VLSI Systems"}],"event":{"name":"2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2013,10,7]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6662534\/6673221\/06673261.pdf?arnumber=6673261","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T22:13:22Z","timestamp":1490220802000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6673261\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2013.6673261","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}