{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:23:48Z","timestamp":1729664628087,"version":"3.28.0"},"reference-count":46,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/vlsi-soc.2013.6673271","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T14:45:44Z","timestamp":1386168344000},"page":"174-179","source":"Crossref","is-referenced-by-count":5,"title":["Spin-electronics based logic fabrics"],"prefix":"10.1109","author":[{"given":"Weisheng","family":"Zhao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacques-Olivier","family":"Klein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhaohao","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yue","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nesrine","family":"Ben Romhane","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Damien","family":"Querlioz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dafine","family":"Ravelosona","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Claude","family":"Chappert","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"crossref","first-page":"1688","DOI":"10.1126\/science.1108813","article-title":"Magnetic domain-wall logic","volume":"309","author":"allwood","year":"2005","journal-title":"Science"},{"doi-asserted-by":"publisher","key":"35","DOI":"10.1016\/j.microrel.2011.07.001"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/TMAG.2011.2150238"},{"doi-asserted-by":"publisher","key":"36","DOI":"10.1109\/TMAG.2012.2194790"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1038\/nature02014"},{"year":"2012","journal-title":"CMOS40 Design Rule Manual","key":"33"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1109\/JSSC.2009.2023192"},{"doi-asserted-by":"publisher","key":"34","DOI":"10.1109\/TED.2011.2178416"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1143\/APEX.1.091301"},{"doi-asserted-by":"publisher","key":"39","DOI":"10.1109\/TMAG.2011.2158294"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/TVLSI.2011.2172644"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1145\/1596543.1596548"},{"doi-asserted-by":"publisher","key":"37","DOI":"10.1109\/TCSI.2012.2220507"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1002\/pssa.200778135"},{"doi-asserted-by":"publisher","key":"38","DOI":"10.1109\/IEDM.2011.6131604"},{"key":"12","first-page":"399","article-title":"Spin-mtj based non-volatile flip-flop","author":"zhao","year":"2007","journal-title":"Proc IEEE Conf Nanotech IEEE NANO"},{"doi-asserted-by":"publisher","key":"21","DOI":"10.1063\/1.4716460"},{"key":"20","doi-asserted-by":"crossref","first-page":"190","DOI":"10.1126\/science.1145799","article-title":"Magnetic domain-wall racetrack memory","volume":"320","author":"parkin","year":"2008","journal-title":"Science"},{"doi-asserted-by":"publisher","key":"43","DOI":"10.1109\/5.58356"},{"doi-asserted-by":"publisher","key":"42","DOI":"10.1103\/PhysRevLett.105.167202"},{"doi-asserted-by":"publisher","key":"41","DOI":"10.1038\/nphys2331"},{"doi-asserted-by":"publisher","key":"40","DOI":"10.1038\/ncomms2386"},{"doi-asserted-by":"publisher","key":"45","DOI":"10.1038\/nphys1968"},{"doi-asserted-by":"publisher","key":"44","DOI":"10.1109\/IJCNN.2012.6252609"},{"doi-asserted-by":"publisher","key":"46","DOI":"10.1109\/TNANO.2012.2202125"},{"key":"22","doi-asserted-by":"crossref","first-page":"499","DOI":"10.1038\/nnano.2012.111","article-title":"Shift registers based on magnetic domain wall ratches with perpentidular anistropy","volume":"7","author":"franken","year":"0","journal-title":"Nature Nanotechnol"},{"doi-asserted-by":"publisher","key":"23","DOI":"10.1063\/1.102730"},{"doi-asserted-by":"publisher","key":"24","DOI":"10.1038\/nature05803"},{"doi-asserted-by":"publisher","key":"25","DOI":"10.1109\/TED.2011.2173498"},{"doi-asserted-by":"publisher","key":"26","DOI":"10.1038\/nnano.2010.31"},{"key":"27","doi-asserted-by":"crossref","first-page":"205","DOI":"10.1126\/science.1120506","article-title":"Majority logic gate for magnetic quantum-dot cellular automata","volume":"311","author":"imre","year":"2006","journal-title":"Science"},{"year":"2012","author":"yoda et al","journal-title":"Progress of STT-MRAM Technology and the Effect on Normally-Off Computing Systems","key":"28"},{"key":"29","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1007\/978-3-642-32770-4_2","article-title":"High performance soc design using magnetic logic and memory","volume":"379","author":"zhao","year":"2012","journal-title":"VLSI-SoC Advanced Research for Systems on Chip IFIP Advances in Information and Communication Technology"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/MC.2003.1250885"},{"year":"2011","key":"2"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/ICECS.2007.4510962"},{"key":"1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-3572-0","author":"brown","year":"1992","journal-title":"Field Programmable Gate Arrays"},{"doi-asserted-by":"publisher","key":"30","DOI":"10.1063\/1.2834714"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/ISSCC.2010.5433948"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/IEDM.2009.5424368"},{"doi-asserted-by":"publisher","key":"32","DOI":"10.1063\/1.3536482"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1038\/nmat2024"},{"key":"31","article-title":"Giant room-Temperature magnetoresistance in singlecrystal Fe\/MgO\/Fe magnetic tunnel junctions","volume":"868","author":"yuasa","year":"2004","journal-title":"Nat Mater"},{"key":"4","article-title":"New computing architectures for Green ICT","author":"duranton","year":"2011","journal-title":"Chist-era Conference"},{"year":"0","journal-title":"Everspin Corporation","key":"9"},{"key":"8","first-page":"304","article-title":"Fully integrated 54nm STT-RAM with the smallest bit cell dimension","author":"chung","year":"2010","journal-title":"Proc IEDM"}],"event":{"name":"2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2013,10,7]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6662534\/6673221\/06673271.pdf?arnumber=6673271","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T23:38:49Z","timestamp":1498088329000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6673271\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2013.6673271","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}