{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,10]],"date-time":"2025-09-10T22:15:41Z","timestamp":1757542541902,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/vlsi-soc.2013.6673274","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T19:45:44Z","timestamp":1386186344000},"page":"192-197","source":"Crossref","is-referenced-by-count":6,"title":["Three-dimensional stacking FPGA architecture using face-to-face integration"],"prefix":"10.1109","author":[{"given":"Tetsuro","family":"Hamada","sequence":"first","affiliation":[]},{"given":"Qian","family":"Zhao","sequence":"additional","affiliation":[]},{"given":"Motoki","family":"Amagasaki","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Iida","sequence":"additional","affiliation":[]},{"given":"Morihiro","family":"Kuga","sequence":"additional","affiliation":[]},{"given":"Toshinori","family":"Sueyoshi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000456"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2007.4402472"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"2009","author":"mishchenko","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1995.580726"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329171"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.59"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796515"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855945"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"12","first-page":"101","article-title":"A design framework for reconfigurable ips with vlsi cads","volume":"112","author":"zhao","year":"2012","journal-title":"Proc of the IEICE Technical Report"}],"event":{"name":"2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2013,10,7]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6662534\/6673221\/06673274.pdf?arnumber=6673274","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T22:41:34Z","timestamp":1490222494000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6673274\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2013.6673274","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}