{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T19:01:39Z","timestamp":1725562899692},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/vlsi-soc.2013.6673279","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T19:45:44Z","timestamp":1386186344000},"page":"222-227","source":"Crossref","is-referenced-by-count":0,"title":["Adapting the columns of storage components for lower static energy dissipation"],"prefix":"10.1109","author":[{"given":"Mehmet Burak","family":"Aykenar","sequence":"first","affiliation":[]},{"given":"Muhammet","family":"Ozgur","sequence":"additional","affiliation":[]},{"given":"Osman Seckin","family":"Simsek","sequence":"additional","affiliation":[]},{"given":"Oguz","family":"Ergin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"crossref","first-page":"752","DOI":"10.1109\/IEDM.1980.189946","article-title":"twin-tub cmos - a technology for vlsi circuits","author":"parrillo","year":"1980","journal-title":"1980 International Electron Devices Meeting"},{"journal-title":"Inside Intel Next Generation Nehalem Microarchitecture","year":"2008","author":"singhal","key":"17"},{"key":"18","doi-asserted-by":"crossref","DOI":"10.1109\/ICICDT.2008.4567245","article-title":"Which is the best dual-port SRAM in 45-nm process technology?-8T, 10T single end, and 10Y differential","author":"noguchi","year":"2008","journal-title":"IEEE International Conference on Integrated Circuit Design and Technology and Tutorial"},{"journal-title":"Standard Performance Evaluation Corporation the SPEC CPU","year":"2006","key":"15"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196116"},{"key":"13","doi-asserted-by":"crossref","DOI":"10.1145\/1105734.1105747","article-title":"Multifacets general execution driven multiprocessor simulator (GEMS) toolset","author":"martin","year":"2005","journal-title":"Computer Architecture News"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2110410"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418914"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.816139"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1109\/4.962281","article-title":"A 0.18-?m CMOS IA-32 processor with a 4-GHz integer execution unit","author":"hinton","year":"2001","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993633"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977306"},{"key":"10","article-title":"Reducing power consumption of embedded processors through register file partitioning and compiler support","author":"guan","year":"2008","journal-title":"Proc Int Conf Application-specific Systems Architectures and Processors"},{"key":"7","article-title":"Using Content-Aware bitcells to reduce static energy dissipation","author":"koc?","year":"0","journal-title":"International Conference on Computer Design"},{"key":"6","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.155259","article-title":"gated-v\/sub dd\/: a circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"5","article-title":"Drowsy caches: Simple techniques for reducing leakage power","author":"flautner","year":"2002","journal-title":"ISCA"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.850127"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/IWIA.2007.12"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344610"}],"event":{"name":"2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2013,10,7]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6662534\/6673221\/06673279.pdf?arnumber=6673279","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T03:38:48Z","timestamp":1498102728000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6673279\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2013.6673279","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}