{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T08:00:04Z","timestamp":1725696004048},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/vlsi-soc.2013.6673301","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T19:45:44Z","timestamp":1386186344000},"page":"322-327","source":"Crossref","is-referenced-by-count":1,"title":["PVT variation detection and compensation methods for high-speed systems"],"prefix":"10.1109","author":[{"given":"Vazgen","family":"Melikyan","sequence":"first","affiliation":[]},{"given":"Abraham","family":"Balabanyan","sequence":"additional","affiliation":[]},{"given":"Armen","family":"Durgaryan","sequence":"additional","affiliation":[]},{"given":"Harutyun","family":"Stepanyan","sequence":"additional","affiliation":[]},{"given":"Karen","family":"Sloyan","sequence":"additional","affiliation":[]},{"given":"Hovik","family":"Musayelyan","sequence":"additional","affiliation":[]},{"given":"Gayane","family":"Markosyan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSE.2008.5276600"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS.2009.5338435"},{"key":"1","first-page":"312","article-title":"Design of CMOS IO drivers with less sensitivity to process, voltage, and temperature variations","author":"gerald jr","year":"2004","journal-title":"Second IEEE International Workshop on Electronic Design Test and Applications Perth Australia"},{"journal-title":"Hspice Application Manual Synopsys Inc -2010","first-page":"196","year":"0","key":"7"},{"key":"6","article-title":"Process-voltage-temperature variation detection and cancelation using on-chip phase-locked loop","author":"melikyan","year":"2012","journal-title":"56th Conference for Electronics Telecomunications Computers Automation and Nuclear Engineering-ETRAN Zlatibor June"},{"journal-title":"PVT Variation Detection and Compensation Circuit\"","year":"2008","author":"divya","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ELNANO.2013.6552085"},{"journal-title":"JEDEC Standard Low Power Double Data Rate 3 (LPDDR3)","first-page":"138","year":"2011","key":"8"}],"event":{"name":"2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2013,10,7]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6662534\/6673221\/06673301.pdf?arnumber=6673301","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T22:27:05Z","timestamp":1490221625000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6673301\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2013.6673301","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}