{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:36:33Z","timestamp":1759332993372,"version":"3.28.0"},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/vlsi-soc.2013.6673310","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T14:45:44Z","timestamp":1386168344000},"page":"364-367","source":"Crossref","is-referenced-by-count":8,"title":["7.72 ppm\/&amp;#x00B0;C, ultralow power, high PSRR CMOS bandgap reference voltage"],"prefix":"10.1109","author":[{"given":"Assia","family":"Hamouda","sequence":"first","affiliation":[]},{"given":"Ruediger","family":"Arnold","sequence":"additional","affiliation":[]},{"given":"Otto","family":"Manck","sequence":"additional","affiliation":[]},{"given":"Nour-Eddine","family":"Bouguechal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","first-page":"271","article-title":"Trimming process and temperature variation in second-order bandgap voltage reference circuits","volume":"42","author":"rajarshi","year":"2010","journal-title":"Elsevier Microelectronic J"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2001.954835"},{"key":"1","first-page":"612","article-title":"Cmos analog circuit design","author":"allen","year":"2002","journal-title":"Oxford Univ Press"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2173267"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1465473"},{"key":"4","doi-asserted-by":"crossref","first-page":"1057","DOI":"10.1016\/j.mejo.2011.06.010","article-title":"A sub 1 v high PSRR CMOS bandgap voltage reference","volume":"42","author":"chahardori","year":"0","journal-title":"Elsevier Microelectronic J"}],"event":{"name":"2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2013,10,7]]},"location":"Istanbul, Turkey","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IFIP\/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6662534\/6673221\/06673310.pdf?arnumber=6673310","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T23:38:46Z","timestamp":1498088326000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6673310\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2013.6673310","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}