{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T08:48:51Z","timestamp":1725612531852},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1109\/vlsi-soc.2014.7004168","type":"proceedings-article","created":{"date-parts":[[2015,1,13]],"date-time":"2015-01-13T20:07:28Z","timestamp":1421179648000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Inference of channel types in micro-architectural models of on-chip communication networks"],"prefix":"10.1109","author":[{"given":"Bernard","family":"van Gastel","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Freek","family":"Verbeek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Julien","family":"Schmaltz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.4204\/EPTCS.114.9"},{"journal-title":"Design of Interconnect Processing Units Spidergon STNoC","year":"2009","author":"coppola","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/95859"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CMPSAC.1998.716629"},{"journal-title":"Introduction to Algorithms","year":"2001","author":"cormen","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_29"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2012.2205998"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s10703-011-0134-0"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-18275-4_16"},{"key":"ref8","article-title":"Automatic generation of deadlock detection algorithms for a family of micro architectural description languages","author":"verbeek","year":"2012","journal-title":"Proc IEEE Int High Level Design Validation and Test Workshop (HLDVT)"},{"key":"ref7","first-page":"223","article-title":"Hunting deadlocks efficiently in microarchitectural models of communication fabrics","author":"verbeek","year":"2011","journal-title":"Proceedings of the International Conference on Formal Methods in Computer-Aided Design Ser FMCAD '11"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2010.5496662"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1193230"}],"event":{"name":"2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2014,10,6]]},"location":"Playa del Carmen, Mexico","end":{"date-parts":[[2014,10,8]]}},"container-title":["2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6996506\/7004150\/07004168.pdf?arnumber=7004168","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T05:21:22Z","timestamp":1490332882000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7004168\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2014.7004168","relation":{},"subject":[],"published":{"date-parts":[[2014,10]]}}}