{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T06:41:10Z","timestamp":1725432070814},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/vlsi-soc.2015.7314384","type":"proceedings-article","created":{"date-parts":[[2015,11,2]],"date-time":"2015-11-02T23:01:11Z","timestamp":1446505271000},"page":"13-18","source":"Crossref","is-referenced-by-count":0,"title":["Analysis and testing on delays with two time frames"],"prefix":"10.1109","author":[{"given":"Masahiro","family":"Fujita","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"184","article-title":"Search State Equivalence for Redundancy Identification and Test Generation","author":"john","year":"1991","journal-title":"International Test Conference (ITC)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.3140"},{"key":"ref10","first-page":"1","article-title":"Model Checking and the State Explosion Problem","author":"clarke","year":"2011","journal-title":"LASER Summer School"},{"key":"ref6","first-page":"19","article-title":"SAT- Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions","author":"satoshi","year":"2012","journal-title":"Asian Test Symposium (ATS)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691102"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035351"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-18275-4_7"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691203"},{"key":"ref2","article-title":"Functional test of small-delay faults using SAT and Craig interpolation","author":"matthias","year":"2012","journal-title":"IEEE International Test Coference (ITC)"},{"key":"ref9","article-title":"Efficient implementation of property directed reachability","author":"en","year":"2011","journal-title":"Formal Methods in Computer-Aided Design (FMCAD)"},{"key":"ref1","first-page":"592","article-title":"An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit","author":"qiu","year":"2003","journal-title":"IEEE International Test Coference (ITC)"}],"event":{"name":"2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2015,10,5]]},"location":"Daejeon, South Korea","end":{"date-parts":[[2015,10,7]]}},"container-title":["2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7304349\/7314373\/07314384.pdf?arnumber=7314384","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T21:15:51Z","timestamp":1490390151000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7314384\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2015.7314384","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}