{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T22:57:52Z","timestamp":1725404272734},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/vlsi-soc.2015.7314399","type":"proceedings-article","created":{"date-parts":[[2015,11,2]],"date-time":"2015-11-02T23:01:11Z","timestamp":1446505271000},"page":"98-103","source":"Crossref","is-referenced-by-count":2,"title":["Prefetch-based dynamic row buffer management for LPDDR2-NVM devices"],"prefix":"10.1109","author":[{"given":"Jaehyun","family":"Park","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donghwa","family":"Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyung Gyu","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2656339"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.1261824"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176872"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"article-title":"Samsung preps 8-Gbit phase-change memory","year":"2011","author":"clarke","key":"ref6"},{"year":"2013","key":"ref5","article-title":"JESD209-F"},{"key":"ref8","article-title":"DynRBLA: A high-performance and energy-efficient row buffer locality-aware caching policy for hybrid memories","author":"yoon","year":"2011","journal-title":"SAFARI Technical Report No 2011-005"},{"article-title":"First volume production phase change memory by micron","year":"2013","author":"krishnamurthy","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2480741.2480746"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742957"}],"event":{"name":"2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2015,10,5]]},"location":"Daejeon, South Korea","end":{"date-parts":[[2015,10,7]]}},"container-title":["2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7304349\/7314373\/07314399.pdf?arnumber=7314399","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T05:09:36Z","timestamp":1490418576000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7314399\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2015.7314399","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}