{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T08:49:51Z","timestamp":1725612591018},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/vlsi-soc.2015.7314400","type":"proceedings-article","created":{"date-parts":[[2015,11,2]],"date-time":"2015-11-02T18:01:11Z","timestamp":1446487271000},"page":"104-109","source":"Crossref","is-referenced-by-count":2,"title":["Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface"],"prefix":"10.1109","author":[{"given":"Jaehyun","family":"Park","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donghwa","family":"Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyung Gyu","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2014.14.6.741"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176872"},{"key":"ref12","first-page":"210","article-title":"Exploring high-performance and energy proportional interface for phase change memory systems","author":"li","year":"2013","journal-title":"2013 IEEE 19th International Symposium on High Performance Computer Architecture"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"journal-title":"First volume production phase change memory by micron","year":"0","author":"krishnamurthy","key":"ref6"},{"year":"2011","author":"clarke","key":"ref5"},{"year":"0","author":"greenberg","key":"ref8"},{"year":"2013","key":"ref7","article-title":"JESD209-F"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2480741.2480746"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"ref9","article-title":"DynRBLA: A high-performance and energy-efficient row buffer locality-aware caching policy for hybrid memories","author":"yoon","year":"2011","journal-title":"SAFARI Technical Report No 2013&#x2013;003"}],"event":{"name":"2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2015,10,5]]},"location":"Daejeon, South Korea","end":{"date-parts":[[2015,10,7]]}},"container-title":["2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7304349\/7314373\/07314400.pdf?arnumber=7314400","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T17:08:30Z","timestamp":1490375310000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7314400\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2015.7314400","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}