{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:45:17Z","timestamp":1761648317790,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/vlsi-soc.2015.7314413","type":"proceedings-article","created":{"date-parts":[[2015,11,2]],"date-time":"2015-11-02T23:01:11Z","timestamp":1446505271000},"page":"183-188","source":"Crossref","is-referenced-by-count":12,"title":["Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM"],"prefix":"10.1109","author":[{"given":"Namhyung","family":"Kim","sequence":"first","affiliation":[]},{"given":"Junwhan","family":"Ahn","sequence":"additional","affiliation":[]},{"given":"Woong","family":"Seo","sequence":"additional","affiliation":[]},{"given":"Kiyoung","family":"Choi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835944"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.179"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2009.5289241"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333717"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781159"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"journal-title":"Macsim Simulator","year":"0","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000075"},{"key":"ref19","article-title":"CACTI 6.0: A tool to model large caches","author":"muralimanohar","year":"2009","journal-title":"HP Tech Report HPL-2009–85"},{"journal-title":"Family 16h Models 00h–0Fh AMD Opteron™ Processor Product Data Sheet Advanced Micro Devices","year":"2014","key":"ref4"},{"key":"ref3","article-title":"Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM","author":"chang","year":"2013","journal-title":"Proc HPCA"},{"key":"ref6","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","author":"wu","year":"2009","journal-title":"Proc DATE"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2013.6629298"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835933"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1145\/1391469.1391610","article-title":"circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement","author":"xiangyu dong","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081626"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2012.2203589"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2032192"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.28"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1145\/1241601.1241616","article-title":"Subsetting the SPEC CPU2006 benchmark suite","volume":"35","author":"phansalkar","year":"2007","journal-title":"ACM SIGARCH Comput Archit News"},{"journal-title":"Technical Report TN-41–01","article-title":"Calculating memory system power for DDR 3","year":"2007","key":"ref25"}],"event":{"name":"2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2015,10,5]]},"location":"Daejeon, South Korea","end":{"date-parts":[[2015,10,7]]}},"container-title":["2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7304349\/7314373\/07314413.pdf?arnumber=7314413","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T22:43:54Z","timestamp":1498257834000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7314413\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2015.7314413","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}