{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,21]],"date-time":"2026-07-21T23:13:17Z","timestamp":1784675597083,"version":"3.55.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/vlsi-soc.2015.7314418","type":"proceedings-article","created":{"date-parts":[[2015,11,2]],"date-time":"2015-11-02T23:01:11Z","timestamp":1446505271000},"page":"213-218","source":"Crossref","is-referenced-by-count":10,"title":["Dual-mode double precision \/ two-parallel single precision floating point multiplier architecture"],"prefix":"10.1109","author":[{"given":"Manish Kumar","family":"Jaiswal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hayden K.-H","family":"So","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"549","DOI":"10.1016\/j.sysarc.2006.03.002","article-title":"Dual-mode floating-point multiplier architectures with parallel operations","volume":"52","author":"akkaa\u00a7","year":"2006","journal-title":"Journal of Systems Architecture"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2003.1231903"},{"key":"ref10","first-page":"349","article-title":"Some schemes for parallel multipliers","volume":"34","author":"dadda","year":"1965","journal-title":"Alta Frequenza"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2011.14"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1973.5009159"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.203"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1109\/ARITH.2007.5","article-title":"A new architecture for multiple-precision floating-point multiply-add fused unit design","author":"huang","year":"2007","journal-title":"Computer Arithmetic 2007 ARITH '07 18th IEEE Symposium"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.45"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2327314"},{"key":"ref2","article-title":"NVIDIA's Next Generation CUDA™ Compute Architecture: Kepler™ GK110","year":"2014","journal-title":"White Paper"},{"key":"ref9","first-page":"1","article-title":"IEEE standard for floating-point arithmetic","year":"2008"},{"key":"ref1","article-title":"AN10902: Using the LPC32xx VFP","year":"2010","journal-title":"Application Note"}],"event":{"name":"2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","location":"Daejeon, South Korea","start":{"date-parts":[[2015,10,5]]},"end":{"date-parts":[[2015,10,7]]}},"container-title":["2015 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7304349\/7314373\/07314418.pdf?arnumber=7314418","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T22:43:55Z","timestamp":1498257835000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7314418\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2015.7314418","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}