{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T05:19:39Z","timestamp":1725772779676},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/vlsi-soc.2016.7753570","type":"proceedings-article","created":{"date-parts":[[2016,11,24]],"date-time":"2016-11-24T21:38:54Z","timestamp":1480023534000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Power and area efficient clock stretching and critical path reshaping for error resilience"],"prefix":"10.1109","author":[{"given":"Mini","family":"Jayakrishnan","sequence":"first","affiliation":[]},{"given":"Alan","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Tae Hyoung","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2220912"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771810"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798256"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416652"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591600"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2015.7314409"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2223467"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref6","first-page":"15","article-title":"A better than worst case circuit design using timing-error speculation and frequency adaptation","author":"moreno","year":"2012","journal-title":"Proc IEEE Int SOC Conf"},{"key":"ref5","first-page":"2","article-title":"Oppotunities and Challenges for Better Than Worst-Case Design","author":"austin","year":"2005","journal-title":"Proc Asia and South Pacific Design Automation Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397342"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457058"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079410"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2057230"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419690"}],"event":{"name":"2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2016,9,26]]},"location":"Tallinn","end":{"date-parts":[[2016,9,28]]}},"container-title":["2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7744451\/7753408\/07753570.pdf?arnumber=7753570","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,5,16]],"date-time":"2020-05-16T21:21:38Z","timestamp":1589664098000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7753570\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2016.7753570","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}