{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T21:20:01Z","timestamp":1725398401701},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/vlsi-soc.2016.7753571","type":"proceedings-article","created":{"date-parts":[[2016,11,24]],"date-time":"2016-11-24T21:38:54Z","timestamp":1480023534000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Optimistic clock adjustment for preventing Better-than-worst-case violations"],"prefix":"10.1109","author":[{"given":"Seyedeh Hanieh","family":"Hashemi","sequence":"first","affiliation":[]},{"given":"Reza","family":"Namazian","sequence":"additional","affiliation":[]},{"given":"Zainalabedin","family":"Navabi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"111:1","article-title":"Dynamic flip-flop conversion to tolerate process variation in low power circuits","author":"nejat","year":"2014","journal-title":"DATE DATE ‘14"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176659"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.72"},{"key":"ref13","first-page":"113","article-title":"A probabilistic and constraint based approach for low power test generation","author":"sabaghian","year":"2012","journal-title":"ATS 2012"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457058"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2015.7314409"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"journal-title":"Atalanta An efficient ATPG for combinational circuits","year":"1993","author":"lee","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.070"},{"key":"ref2","first-page":"1","article-title":"Darp: dynamically adaptable resilient pipeline design in microprocessors","author":"chen","year":"2014","journal-title":"DATE 2014"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488860"},{"article-title":"Dynamic flip-flop conversion: A time-borrowing method for performance","year":"0","author":"nejat","key":"ref9"}],"event":{"name":"2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2016,9,26]]},"location":"Tallinn, Estonia","end":{"date-parts":[[2016,9,28]]}},"container-title":["2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7744451\/7753408\/07753571.pdf?arnumber=7753571","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,12,17]],"date-time":"2016-12-17T08:38:20Z","timestamp":1481963900000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7753571\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2016.7753571","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}