{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T06:21:33Z","timestamp":1725517293440},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/vlsi-soc.2016.7753572","type":"proceedings-article","created":{"date-parts":[[2016,11,24]],"date-time":"2016-11-24T21:38:54Z","timestamp":1480023534000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs"],"prefix":"10.1109","author":[{"family":"Yi Zhao","sequence":"first","affiliation":[]},{"given":"Saqib","family":"Khursheed","sequence":"additional","affiliation":[]},{"given":"Bashir M.","family":"Al-Hashimi","sequence":"additional","affiliation":[]},{"family":"Zhiwen Zhao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation","author":"fangming","year":"2012","journal-title":"DAC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.1257591"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560164"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074070"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055171"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2014.7152167"},{"key":"ref17","first-page":"1096","article-title":"Performance maximized interlayer via planning for 3D ICs","author":"lu","year":"2007","journal-title":"ASIC 2007"},{"key":"ref18","article-title":"Via assignment algorithm for hierarchical 3D placement","author":"yan","year":"2005","journal-title":"Proceedings of Communications Circuits and Systems"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2050012"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681638"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241859"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.37"},{"key":"ref5","first-page":"166","article-title":"TSV Redundancy: Architecture and Design Issues in 3D IC","author":"hsieh","year":"2010"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2010.5490883"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488824"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1412587.1412593"},{"key":"ref9","article-title":"Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA","author":"gyujei","year":"2011","journal-title":"ECTC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127928"},{"key":"ref22","article-title":"Online fault tolerance technique for TSV-based 3D-IC","author":"zhao","year":"2014","journal-title":"Very Large Scale Integration (VLSI) Systems IEEE Transactions on"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2201760"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358084"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785580"},{"journal-title":"MCNC\/GSRC benchmarks","year":"0","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2226584"}],"event":{"name":"2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2016,9,26]]},"location":"Tallinn, Estonia","end":{"date-parts":[[2016,9,28]]}},"container-title":["2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7744451\/7753408\/07753572.pdf?arnumber=7753572","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,12,20]],"date-time":"2016-12-20T03:48:44Z","timestamp":1482205724000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7753572\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2016.7753572","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}