{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:42:42Z","timestamp":1730302962729,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/vlsi-soc.2016.7753577","type":"proceedings-article","created":{"date-parts":[[2016,11,24]],"date-time":"2016-11-24T16:38:54Z","timestamp":1480005534000},"page":"1-6","source":"Crossref","is-referenced-by-count":8,"title":["Synthesis on switching lattices of Dimension-reducible Boolean functions"],"prefix":"10.1109","author":[{"given":"Anna","family":"Bernasconi","sequence":"first","affiliation":[]},{"given":"Valentina","family":"Ciriani","sequence":"additional","affiliation":[]},{"given":"Luca","family":"Frontini","sequence":"additional","affiliation":[]},{"given":"Gabriella","family":"Trucco","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2010.5642674"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2006.46"},{"key":"ref10","article-title":"Logic Synthesis and Optimization Benchmarks User Guide Version 3.0","author":"yang","year":"1991","journal-title":"User Guide Microelectronic Center"},{"key":"ref6","first-page":"265","article-title":"Auto symmetric and dimension reducible multiple-valued functions","volume":"23","author":"bernasconi","year":"2014","journal-title":"Multiple-Valued Logic and Soft Computing"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1929943.1929945"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2661632"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818121"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.170"},{"journal-title":"Principles of CMOS VLSI Design","year":"1993","author":"weste","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009040"}],"event":{"name":"2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2016,9,26]]},"location":"Tallinn, Estonia","end":{"date-parts":[[2016,9,28]]}},"container-title":["2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7744451\/7753408\/07753577.pdf?arnumber=7753577","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,12,19]],"date-time":"2016-12-19T22:33:09Z","timestamp":1482186789000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7753577\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2016.7753577","relation":{},"subject":[],"published":{"date-parts":[[2016,9]]}}}