{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T05:05:09Z","timestamp":1725167109509},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/vlsi-soc.2017.8203467","type":"proceedings-article","created":{"date-parts":[[2017,12,14]],"date-time":"2017-12-14T22:13:26Z","timestamp":1513289606000},"source":"Crossref","is-referenced-by-count":8,"title":["Multiple reset domains verification using assertion based verification"],"prefix":"10.1109","author":[{"given":"Islam","family":"Ahmed","sequence":"first","affiliation":[]},{"given":"Khaled","family":"Nouh","sequence":"additional","affiliation":[]},{"given":"Amr","family":"Abbas","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","article-title":"Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using System Verilog Assertions","author":"litterick","year":"2006","journal-title":"DVCON"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796554"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2003.1199169"},{"key":"ref6","article-title":"Low Power Verification Methodology Using UPF","author":"bembaron","year":"2011","journal-title":"DVCON"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FAMCAD.2007.22"},{"key":"ref8","article-title":"Reset Testing Made Simple with UVM Phases","author":"hunter","year":"2013","journal-title":"SNUG"},{"key":"ref7","article-title":"Power Aware CDC Verification at RTL for Faster SoC Verification Closure","author":"chakraborty","year":"2014","journal-title":"DVCon India"},{"key":"ref2","article-title":"Addressing the Challenges of Reset Verification in soc Designs","author":"kwok","year":"2015","journal-title":"DVCON"},{"key":"ref9","first-page":"1","author":"melnychenko","year":"2014","journal-title":"Towards formal verification of reset sequence in fully asynchronous digital circuits"},{"key":"ref1","year":"0","journal-title":"ARM&#x00AE; Cortex&#x00AE;-A17 MPCore Processor Technical Reference Manual Revision rl p0"}],"event":{"name":"2017 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","location":"Abu Dhabi","start":{"date-parts":[[2017,10,23]]},"end":{"date-parts":[[2017,10,25]]}},"container-title":["2017 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8168766\/8203442\/08203467.pdf?arnumber=8203467","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,1,23]],"date-time":"2018-01-23T20:33:17Z","timestamp":1516739597000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8203467\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2017.8203467","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}