{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T05:11:27Z","timestamp":1777439487628,"version":"3.51.4"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/vlsi-soc.2019.8920318","type":"proceedings-article","created":{"date-parts":[[2019,12,6]],"date-time":"2019-12-06T03:10:45Z","timestamp":1575601845000},"page":"317-322","source":"Crossref","is-referenced-by-count":3,"title":["Double Data Rate Dynamic Edge-Coded Signaling for Low-Power IoT Communication"],"prefix":"10.1109","author":[{"given":"Shahzad","family":"Muzaffar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ibrahim Abe M.","family":"Elfadel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2178557"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2007.137"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572161"},{"key":"ref13","first-page":"373","article-title":"A 2.5-12.5Gbps Interpolator-based Clock and Data Recovery Circuit for FPGA","author":"soh","year":"2012","journal-title":"Asia Symposium on Quality Electronic Design (ASQED)"},{"key":"ref4","year":"2008","journal-title":"Overview of 1-wire technology and its use"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IIH-MSP.2014.211"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1070"},{"key":"ref5","first-page":"228","article-title":"Monolithic Data Circuit-Terminating Unit (DCU) for a One-Wire Vehicle Network","author":"dos reis filho","year":"1998","journal-title":"Proc 24th Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref8","article-title":"Dynamic Edge-coded Protocols for Lowpower, Device-to-Device Communication","author":"muzaffar","year":"2019","journal-title":"ACM Transactions on Sensor Networks (TOSN)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2017.8203491"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SCC.2014.27"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICEBE.2010.42"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560319"}],"event":{"name":"2019 IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)","location":"Cuzco, Peru","start":{"date-parts":[[2019,10,6]]},"end":{"date-parts":[[2019,10,9]]}},"container-title":["2019 IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8910139\/8920290\/08920318.pdf?arnumber=8920318","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T10:50:30Z","timestamp":1658141430000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8920318\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2019.8920318","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}