{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T17:09:55Z","timestamp":1765040995949,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/vlsi-soc.2019.8920330","type":"proceedings-article","created":{"date-parts":[[2019,12,6]],"date-time":"2019-12-06T08:10:45Z","timestamp":1575619845000},"page":"52-57","source":"Crossref","is-referenced-by-count":8,"title":["Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions"],"prefix":"10.1109","author":[{"given":"Y. Serhan","family":"Gener","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sezer","family":"Goren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H. Fatih","family":"Ugurdag","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Multipartite tables in JBits for the evaluation of functions on FPGA","author":"detrey","year":"2001","journal-title":"Diss INRIA"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.54"},{"journal-title":"The multipartite method for function evaluation","year":"2017","author":"dinechin","key":"ref10"},{"key":"ref6","first-page":"171","article-title":"Area-efficient look-up tables for semi-randomly accessible functions","author":"unlu","year":"2014","journal-title":"Proc of WSEAS Recent Advances in Electrical Engineering"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.44"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2574314"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1952.273898"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2386232"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1995.465381"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2011.6116419"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"858","DOI":"10.1109\/TC.2012.43","article-title":"A Memory-efficient tables-and-additions method for accurate computation of elementary functions","volume":"62","author":"lih","year":"2013","journal-title":"IEEE Trans on Computers"}],"event":{"name":"2019 IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2019,10,6]]},"location":"Cuzco, Peru","end":{"date-parts":[[2019,10,9]]}},"container-title":["2019 IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8910139\/8920290\/08920330.pdf?arnumber=8920330","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T14:47:15Z","timestamp":1658155635000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8920330\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc.2019.8920330","relation":{},"subject":[],"published":{"date-parts":[[2019,10]]}}}