{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:10:22Z","timestamp":1767262222198,"version":"3.37.3"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000844","name":"European Space Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000844","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,3]]},"DOI":"10.1109\/vlsi-soc54400.2022.9939566","type":"proceedings-article","created":{"date-parts":[[2022,11,8]],"date-time":"2022-11-08T20:41:50Z","timestamp":1667940110000},"page":"1-4","source":"Crossref","is-referenced-by-count":16,"title":["Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI\/ML in Space Applications"],"prefix":"10.1109","author":[{"given":"Vasileios","family":"Leon","sequence":"first","affiliation":[{"name":"National Technical University of Athens,Athens,Greece,15780"}]},{"given":"George","family":"Lentaris","sequence":"additional","affiliation":[{"name":"National Technical University of Athens,Athens,Greece,15780"}]},{"given":"Dimitrios","family":"Soudris","sequence":"additional","affiliation":[{"name":"National Technical University of Athens,Athens,Greece,15780"}]},{"given":"Simon","family":"Vellas","sequence":"additional","affiliation":[{"name":"OHB-Hellas,Marousi,Greece,15124"}]},{"given":"Mathieu","family":"Bernou","sequence":"additional","affiliation":[{"name":"OHB-Hellas,Marousi,Greece,15124"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TGRS.2021.3125567"},{"key":"ref11","first-page":"1","article-title":"Benchmarking Machine Learning on The Myriad X Processor Onboard the ISS","author":"dunkel","year":"0","journal-title":"Int’l Space Station Research and Development Conf"},{"key":"ref12","first-page":"1","article-title":"NASA SpaceCube Edge TPU SmallSat Card for Autonomous Operations and Onboard Science-Data Analysis","author":"goodwill","year":"2021","journal-title":"AIAA\/USU Conf on Small Satellites"},{"year":"0","journal-title":"EO and GNSS Market Report","key":"ref13"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1016\/j.micpro.2020.103143"},{"year":"0","journal-title":"TE08XX Zynq UltraScale","key":"ref15"},{"year":"0","author":"xilinx","journal-title":"XQRKU060 FPGA","key":"ref16"},{"year":"0","author":"xplore","journal-title":"RHBD FPGAs","key":"ref17"},{"year":"0","author":"coral","journal-title":"TPU USB Accelerator","key":"ref18"},{"year":"0","author":"intel","journal-title":"VPU NCS2 Accelerator","key":"ref19"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/ACCESS.2021.3114502"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/AHS.2018.8541492"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/ACCESS.2020.2983308"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ACCESS.2020.2980767"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/3440885"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.3390\/aerospace7110159"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/JPROC.2018.2802438"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/MAES.2020.3008468"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ICECS53924.2021.9665462"},{"year":"0","author":"ubotica","journal-title":"CogniSat","key":"ref20"}],"event":{"name":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2022,10,3]]},"location":"Patras, Greece","end":{"date-parts":[[2022,10,5]]}},"container-title":["2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9939277\/9939284\/09939566.pdf?arnumber=9939566","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T20:22:01Z","timestamp":1669666921000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9939566\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc54400.2022.9939566","relation":{},"subject":[],"published":{"date-parts":[[2022,10,3]]}}}