{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:44:19Z","timestamp":1730303059917,"version":"3.28.0"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,3]]},"DOI":"10.1109\/vlsi-soc54400.2022.9939593","type":"proceedings-article","created":{"date-parts":[[2022,11,8]],"date-time":"2022-11-08T15:41:50Z","timestamp":1667922110000},"page":"1-2","source":"Crossref","is-referenced-by-count":1,"title":["Design and characterisation of a Physically Unclonable Function on FPGA using second-order compensated measurement"],"prefix":"10.1109","author":[{"given":"J.","family":"Fernandez-Aragon","sequence":"first","affiliation":[{"name":"Universidad de Zaragoza,Group of Electronic Design,Zaragoza,Spain"}]},{"given":"G.","family":"Diez-Senorans","sequence":"additional","affiliation":[{"name":"Universidad de Zaragoza,Group of Electronic Design,Zaragoza,Spain"}]},{"given":"M.","family":"Garcia-Bosque","sequence":"additional","affiliation":[{"name":"Universidad de Zaragoza,Group of Electronic Design,Zaragoza,Spain"}]},{"given":"S.","family":"Celma","sequence":"additional","affiliation":[{"name":"Universidad de Zaragoza,Group of Electronic Design,Zaragoza,Spain"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Implementación de arquitectura ROPUF en FPGA para identificación segura de dispositivos","volume":"7","author":"diez-senorans","year":"2019","journal-title":"Revista Jornada de Jóvenes Investigadores del I3A"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD49232.2020.9218404"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272361"},{"journal-title":"Physically Unclonable Functions Concept and Constructions","year":"2012","author":"maes","key":"ref2"},{"journal-title":"Physical Unclonable Functions in Theory and Practice","year":"2013","author":"hofer","key":"ref1"}],"event":{"name":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2022,10,3]]},"location":"Patras, Greece","end":{"date-parts":[[2022,10,5]]}},"container-title":["2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9939277\/9939284\/09939593.pdf?arnumber=9939593","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T15:21:50Z","timestamp":1669648910000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9939593\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,3]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc54400.2022.9939593","relation":{},"subject":[],"published":{"date-parts":[[2022,10,3]]}}}