{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T07:44:31Z","timestamp":1725608671060},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,3]]},"DOI":"10.1109\/vlsi-soc54400.2022.9939606","type":"proceedings-article","created":{"date-parts":[[2022,11,8]],"date-time":"2022-11-08T20:41:50Z","timestamp":1667940110000},"page":"1-2","source":"Crossref","is-referenced-by-count":0,"title":["Automated Framework for Fast Synthesis of Approximate Hardware Accelerators"],"prefix":"10.1109","author":[{"given":"Muhammad","family":"Awais","sequence":"first","affiliation":[{"name":"Quaid-e-Awam University,Department of Artificial Intelligence,Pakistan"}]},{"given":"Marco","family":"Platzner","sequence":"additional","affiliation":[{"name":"Paderborn University,Department of Computer Science,Germany"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3317998"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/WAINA.2016.172"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342067"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2018.8645026"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCIAIG.2012.2186810"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967003"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.374"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926993"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2019.04.003"}],"event":{"name":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2022,10,3]]},"location":"Patras, Greece","end":{"date-parts":[[2022,10,5]]}},"container-title":["2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9939277\/9939284\/09939606.pdf?arnumber=9939606","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T20:21:56Z","timestamp":1669666916000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9939606\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,3]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc54400.2022.9939606","relation":{},"subject":[],"published":{"date-parts":[[2022,10,3]]}}}