{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T18:00:25Z","timestamp":1776276025309,"version":"3.50.1"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,3]]},"DOI":"10.1109\/vlsi-soc54400.2022.9939616","type":"proceedings-article","created":{"date-parts":[[2022,11,8]],"date-time":"2022-11-08T20:41:50Z","timestamp":1667940110000},"page":"1-4","source":"Crossref","is-referenced-by-count":5,"title":["High-Performance Hardware Accelerators for Next Generation On-Board Data Processing"],"prefix":"10.1109","author":[{"given":"Antonis","family":"Paschalis","sequence":"first","affiliation":[{"name":"National & Kapodistrian University of Athens (NKUA),Dept. of Informatics and Telecommunications,Athens,Greece"}]},{"given":"Panagiotis","family":"Chatziantoniou","sequence":"additional","affiliation":[{"name":"National & Kapodistrian University of Athens (NKUA),Dept. of Informatics and Telecommunications,Athens,Greece"}]},{"given":"Dimitris","family":"Theodoropoulos","sequence":"additional","affiliation":[{"name":"National & Kapodistrian University of Athens (NKUA),Dept. of Informatics and Telecommunications,Athens,Greece"}]},{"given":"Antonis","family":"Tsigkanos","sequence":"additional","affiliation":[{"name":"National & Kapodistrian University of Athens (NKUA),Dept. of Informatics and Telecommunications,Athens,Greece"}]},{"given":"Nektarios","family":"Kranitis","sequence":"additional","affiliation":[{"name":"National & Kapodistrian University of Athens (NKUA),Dept. of Aerospace Science & Technology,Psahna Evias,Greece"}]}],"member":"263","reference":[{"key":"ref10","year":"2014","journal-title":"Erasure Correcting Codes for Use in Near-Earth and Deep Space Communications CCSDS Experimental Specification 131 5-O-1"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2019.2916271"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2021.3131543"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2018.2854412"},{"key":"ref14","year":"2020","journal-title":"Low-Complexity Lossless and near-Lossless Multispectral and Hyperspectral Image Compression - Draft Informational Report CCSDS 120 2-G-2"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.3390\/rs13214388"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2022.3173583"},{"key":"ref6","year":"2017","journal-title":"TM Synchronization and Channel Coding CCSDS Recommended Standard 131 0-B-3"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TGRS.2022.3160646"},{"key":"ref8","year":"2019","journal-title":"Optical Communications Coding and Synchronization CCSDS Recommended Standard 142 0-B-1"},{"key":"ref7","year":"2017","journal-title":"TC Synchronization and Channel Coding CCSDS Recommended Standard 231 0-B-3"},{"key":"ref2","year":"2012","journal-title":"Lossless Multispectral and Hyperspectral Image Compression Issue 1 CCSDS Recommended Standard 123 0-B-1"},{"key":"ref1","year":"2019","journal-title":"Low-Complexity Lossless and near-Lossless Multispectral and Hyperspectral Image Compression Issue 2 CCSDS Recommended Standard 123 0-B-2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2975050"}],"event":{"name":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","location":"Patras, Greece","start":{"date-parts":[[2022,10,3]]},"end":{"date-parts":[[2022,10,5]]}},"container-title":["2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9939277\/9939284\/09939616.pdf?arnumber=9939616","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T20:22:01Z","timestamp":1669666921000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9939616\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc54400.2022.9939616","relation":{},"subject":[],"published":{"date-parts":[[2022,10,3]]}}}