{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,26]],"date-time":"2025-04-26T19:06:14Z","timestamp":1745694374450,"version":"3.37.3"},"reference-count":32,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100010002","name":"Ministry of Education","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100010002","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,3]]},"DOI":"10.1109\/vlsi-soc54400.2022.9939622","type":"proceedings-article","created":{"date-parts":[[2022,11,8]],"date-time":"2022-11-08T20:41:50Z","timestamp":1667940110000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection"],"prefix":"10.1109","author":[{"given":"Nicolas","family":"Gerlin","sequence":"first","affiliation":[{"name":"Infineon Technologies,AG,Germany"}]},{"given":"Endri","family":"Kaja","sequence":"additional","affiliation":[{"name":"Infineon Technologies,AG,Germany"}]},{"given":"Monideep","family":"Bora","sequence":"additional","affiliation":[{"name":"Infineon Technologies,AG,Germany"}]},{"given":"Keerthikumara","family":"Devarajegowda","sequence":"additional","affiliation":[{"name":"Infineon Technologies,AG,Germany"}]},{"given":"Dominik","family":"Stoffel","sequence":"additional","affiliation":[{"name":"Technische Universität,Kaiserslautern,Germany"}]},{"given":"Wolfgang","family":"Kunz","sequence":"additional","affiliation":[{"name":"Technische Universität,Kaiserslautern,Germany"}]},{"given":"Wolfgang","family":"Ecker","sequence":"additional","affiliation":[{"name":"Infineon Technologies,AG,Germany"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2018.8644957"},{"article-title":"Rocket chip generator","year":"2022","author":"alliance","key":"ref31"},{"year":"2022","key":"ref30","article-title":"Ibex"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3342195.3387532"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3112202"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2018.00025"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3022841"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586207"},{"key":"ref15","first-page":"1","article-title":"S-blocks: Lightweight and trusted virtual security function with sgx","author":"wang","year":"2020","journal-title":"IEEE Transactions on Cloud Computing"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/EuroSP.2019.00023"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2018.2861756"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST51057.2020.9358260"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2987617"},{"key":"ref28","article-title":"The definitive guide to the ARM Cortex-M3","author":"yiu","year":"2009","journal-title":"Newnes"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2018.8607169"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586264"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/EDCC.2019.00018"},{"key":"ref6","article-title":"Real-time thread isolation and trusted execution on embedded risc-v","author":"lindemer","year":"2020","journal-title":"Proceedings of the International Workshop on Secure RISC-V Architecture Design Exploration (SECRISC-V)"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3058162"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2018.2805734"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2487726.2488368"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SPW53761.2021.00036"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763291"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CIC.2016.065"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/SIES.2013.6601495"},{"key":"ref20","article-title":"Software-based off-chip memory protection for risc-v trusted execution environments","author":"andrade","year":"2020","journal-title":"UC Berkeley"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431639"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2018.8516874"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2022.i1.28-68"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3024853"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2016.7753576"},{"key":"ref25","article-title":"The risc-v instruction set manual, volume ii: Privileged architecture","author":"waterman","year":"2021","journal-title":"RISC-V International"}],"event":{"name":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2022,10,3]]},"location":"Patras, Greece","end":{"date-parts":[[2022,10,5]]}},"container-title":["2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9939277\/9939284\/09939622.pdf?arnumber=9939622","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T20:22:10Z","timestamp":1669666930000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9939622\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,3]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc54400.2022.9939622","relation":{},"subject":[],"published":{"date-parts":[[2022,10,3]]}}}