{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T21:16:39Z","timestamp":1725743799115},"reference-count":17,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,3]]},"DOI":"10.1109\/vlsi-soc54400.2022.9939630","type":"proceedings-article","created":{"date-parts":[[2022,11,8]],"date-time":"2022-11-08T20:41:50Z","timestamp":1667940110000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge"],"prefix":"10.1109","author":[{"given":"Theo","family":"Soriano","sequence":"first","affiliation":[{"name":"University of Montpellier, CNRS,LIRMM,Montpellier,France"}]},{"given":"David","family":"Novo","sequence":"additional","affiliation":[{"name":"University of Montpellier, CNRS,LIRMM,Montpellier,France"}]},{"given":"Guillaume","family":"Prenat","sequence":"additional","affiliation":[{"name":"University of Grenoble-Alpes, CNRS, CEA,SPINTEC,Grenoble,France"}]},{"given":"Gregory Di","family":"Pendina","sequence":"additional","affiliation":[{"name":"University of Grenoble-Alpes, CNRS, CEA,SPINTEC,Grenoble,France"}]},{"given":"Pascal","family":"Benoit","sequence":"additional","affiliation":[{"name":"University of Montpellier, CNRS,LIRMM,Montpellier,France"}]}],"member":"263","reference":[{"key":"ref10","article-title":"An FPGA-accelerated fully nonvolatile MCU for sensor-node applications in 40nm CMOS\/MTJ-hybrid technology achieving 47.14?w operation at 200MHz","author":"natsui","year":"2019","journal-title":"Proceedings of ISSCC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116321"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/RSP53691.2021.9806230"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.2008.113"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774666"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2015.21"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194633"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SAS.2019.8706095"},{"key":"ref4","article-title":"A ferroelectric nonvolatile processor with 46 ?s system-level wake-up time and 14 ?s sleep time for energy harvesting applications","author":"su","year":"2016","journal-title":"IEEE TCAS1"},{"key":"ref3","article-title":"An FRAM-based nonvolatile logic MCU SoC exhibiting 100% digital state retention at VDD = 0 V achieving zero leakage with <400-ns wakeup time for ULP applications","author":"khanna","year":"2013","journal-title":"IEEE JSSC"},{"key":"ref6","article-title":"A 462GOPs\/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory","author":"su","year":"2017","journal-title":"Proceedings of the IEEE Symposium on VLSI"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2884349"},{"key":"ref8","article-title":"A 43pJ\/cycle non-volatile microcontroller with 4.7 ?s shutdown\/ wake-up integrating 2.3-bit\/cell resistive RAM and resilience techniques","author":"wu","year":"2019","journal-title":"Proceedings of ISSCC"},{"key":"ref7","article-title":"A 65-nm ReRAM-enabled nonvolatile processor with time-space domain adaption and self-write-termination achieving >4x faster clock frequency and >6x higher restore speed","author":"wang","year":"2017","journal-title":"IEEE JSSC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746342"},{"key":"ref1","article-title":"Ultra low-power integrated systems for the internet-of-things","author":"patrigeon","year":"2020","journal-title":"Ph D dissertation Univ Montpellier"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757392"}],"event":{"name":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2022,10,3]]},"location":"Patras, Greece","end":{"date-parts":[[2022,10,5]]}},"container-title":["2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9939277\/9939284\/09939630.pdf?arnumber=9939630","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T20:22:14Z","timestamp":1669666934000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9939630\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,3]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc54400.2022.9939630","relation":{},"subject":[],"published":{"date-parts":[[2022,10,3]]}}}