{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:44:26Z","timestamp":1730303066235,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,3]]},"DOI":"10.1109\/vlsi-soc54400.2022.9939631","type":"proceedings-article","created":{"date-parts":[[2022,11,8]],"date-time":"2022-11-08T15:41:50Z","timestamp":1667922110000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory"],"prefix":"10.1109","author":[{"given":"Christopher","family":"Chuvalas","sequence":"first","affiliation":[{"name":"University of Cincinnati,Cincinnati,Ohio,USA"}]},{"given":"Ranga","family":"Vemuri","sequence":"additional","affiliation":[{"name":"University of Cincinnati,Cincinnati,Ohio,USA"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1609\/aimag.v33i1.2395"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.18"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927405"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC2018.2018.00043"},{"key":"ref14","article-title":"Optimizing Memory Performance of Xilinx FPGAs under Vitis","author":"li","year":"2020","journal-title":"arXiv 2010 08916 [cs]"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL50879.2020.00062"},{"first-page":"45","article-title":"Alveo U280 Data Center Accelerator Card User Guide","year":"2019","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1049\/cje.2019.06.015"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/S1571-0653(04)00333-6"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-31612-8_3"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2652220"},{"key":"ref3","article-title":"Detecting hardware trojans: a tale of two techniques","author":"malik","year":"2016","journal-title":"Institute of Electrical and Electronics Engineers (IEEE)"},{"key":"ref6","first-page":"30","article-title":"Solver description of dimetheus v. 1.7 sat competition 2013","author":"gebleske","year":"2013","journal-title":"Proceedings of SAT Competition 2013"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380697"},{"key":"ref8","first-page":"265","article-title":"Caffeinated FPGAs: FPGA framework for convolutional neural networks","author":"di cecco","year":"2017","journal-title":"Proceedings of the 2016 International Conference on Field-Programmable Technology FPT 2016"},{"first-page":"15","article-title":"Alveo U280 Data Center Accelerator Card Data Sheet","year":"2021","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04138-9_26"},{"first-page":"707","article-title":"Vitis Unified Software Platform Documentation: Application Acceleration Development","year":"2021","key":"ref9"},{"article-title":"Walksat benchmark generator","year":"0","author":"kautz","key":"ref20"},{"key":"ref22","article-title":"SAT COMPETITION 2020 Solver and Benchmark Descriptions","author":"belov","year":"2020","journal-title":"Tech Rep"},{"key":"ref21","volume":"b 2018 1","author":"heule","year":"2018","journal-title":"Proceedings of sat competition 2018 Solver and benchmark descriptions"}],"event":{"name":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2022,10,3]]},"location":"Patras, Greece","end":{"date-parts":[[2022,10,5]]}},"container-title":["2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9939277\/9939284\/09939631.pdf?arnumber=9939631","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T15:22:19Z","timestamp":1669648939000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9939631\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,3]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc54400.2022.9939631","relation":{},"subject":[],"published":{"date-parts":[[2022,10,3]]}}}