{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,2]],"date-time":"2026-02-02T14:14:18Z","timestamp":1770041658662,"version":"3.49.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T00:00:00Z","timestamp":1664755200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100009224","name":"Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100009224","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,3]]},"DOI":"10.1109\/vlsi-soc54400.2022.9939636","type":"proceedings-article","created":{"date-parts":[[2022,11,8]],"date-time":"2022-11-08T20:41:50Z","timestamp":1667940110000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing"],"prefix":"10.1109","author":[{"given":"Michael","family":"Keyser","sequence":"first","affiliation":[{"name":"University of Utah,Salt Lake City,UT,USA"}]},{"given":"Roman","family":"Gauchi","sequence":"additional","affiliation":[{"name":"University of Utah,Salt Lake City,UT,USA"}]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[{"name":"University of Utah,Salt Lake City,UT,USA"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Open-source 10-nm TIGFET standard cell library","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1021\/nl025875l"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1021\/acsnano.8b02739"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1021\/nl203094h"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047045"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2765491.2765503"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1021\/acsnano.6b07531"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2333675"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2017.8053723"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2020.2965119"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2018.8638608"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479004"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2359112"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920358"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2021.3070475"},{"key":"ref7","article-title":"Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs","author":"zou","year":"2011","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2778504"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3089671"},{"key":"ref20","article-title":"An open-source three-independent-gate fet standard cell library for mixed logic synthesis","author":"gauchi","year":"2022","journal-title":"IEEE Int Symp on Circuits and Systems (ISCAS)"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2358884"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228369"},{"key":"ref24","article-title":"Picorv32 - a size-optimized risc-v cpu","author":"wolf","year":"0"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717782"}],"event":{"name":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","location":"Patras, Greece","start":{"date-parts":[[2022,10,3]]},"end":{"date-parts":[[2022,10,5]]}},"container-title":["2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9939277\/9939284\/09939636.pdf?arnumber=9939636","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,28]],"date-time":"2022-11-28T20:21:55Z","timestamp":1669666915000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9939636\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,3]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc54400.2022.9939636","relation":{},"subject":[],"published":{"date-parts":[[2022,10,3]]}}}