{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,11]],"date-time":"2025-01-11T05:33:31Z","timestamp":1736573611471,"version":"3.32.0"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,10,6]],"date-time":"2024-10-06T00:00:00Z","timestamp":1728172800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,10,6]],"date-time":"2024-10-06T00:00:00Z","timestamp":1728172800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,10,6]]},"DOI":"10.1109\/vlsi-soc62099.2024.10767784","type":"proceedings-article","created":{"date-parts":[[2024,12,3]],"date-time":"2024-12-03T18:53:02Z","timestamp":1733251982000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation"],"prefix":"10.1109","author":[{"given":"Assia","family":"El-Hadbi","sequence":"first","affiliation":[{"name":"Institut National des Postes et Télécommunications, STRS Lab.,Rabat,Morocco"}]},{"given":"Oussama","family":"Elissati","sequence":"additional","affiliation":[{"name":"Institut National des Postes et Télécommunications, STRS Lab.,Rabat,Morocco"}]},{"given":"Laurent","family":"Fesquet","sequence":"additional","affiliation":[{"name":"Université Grenoble Alpes,CNRS, Grenoble INP, TIMA Lab.,Grenoble,France"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014709"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2503718"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/EBCCSP.2019.8836857"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2016.2534670"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2020.2984929"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/19.552156"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2698479"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2569626"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2017.8010166"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-018-1223-4"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/I2MTC50364.2021.9460031"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2017.11.022"}],"event":{"name":"2024 IFIP\/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2024,10,6]]},"location":"Tanger, Morocco","end":{"date-parts":[[2024,10,9]]}},"container-title":["2024 IFIP\/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10767775\/10767782\/10767784.pdf?arnumber=10767784","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T19:55:28Z","timestamp":1736538928000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10767784\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,6]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc62099.2024.10767784","relation":{},"subject":[],"published":{"date-parts":[[2024,10,6]]}}}