{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T07:23:34Z","timestamp":1760081014795,"version":"3.32.0"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,10,6]],"date-time":"2024-10-06T00:00:00Z","timestamp":1728172800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,10,6]],"date-time":"2024-10-06T00:00:00Z","timestamp":1728172800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001843","name":"Science and Engineering Research Board (SERB)","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001843","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,10,6]]},"DOI":"10.1109\/vlsi-soc62099.2024.10767805","type":"proceedings-article","created":{"date-parts":[[2024,12,3]],"date-time":"2024-12-03T18:53:02Z","timestamp":1733251982000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Low Power Network-on-Chip Architecture Design Technique"],"prefix":"10.1109","author":[{"given":"Tejas","family":"Musale","sequence":"first","affiliation":[{"name":"BITS Pilani,Department of Electrical and Electronics Engineering,India"}]},{"given":"Arun","family":"Ganti","sequence":"additional","affiliation":[{"name":"BITS Pilani,Department of Computer Science and Information Systems,India"}]},{"given":"Ankur","family":"Gogoi","sequence":"additional","affiliation":[{"name":"Galgotias University,Uttar Pradesh,India"}]},{"given":"Kanchan","family":"Manna","sequence":"additional","affiliation":[{"name":"BITS Pilani,Department of Computer Science and Information Systems,India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310759"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2010.5642624"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2015.7245728"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2015.2402197"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572369"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2018.8704068"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.5"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253687"},{"volume-title":"An architectural power model for networks on chip","year":"2023","author":"Agrawal","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.58"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3073763.3073767"}],"event":{"name":"2024 IFIP\/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)","start":{"date-parts":[[2024,10,6]]},"location":"Tanger, Morocco","end":{"date-parts":[[2024,10,9]]}},"container-title":["2024 IFIP\/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10767775\/10767782\/10767805.pdf?arnumber=10767805","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T19:55:05Z","timestamp":1736538905000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10767805\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,6]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc62099.2024.10767805","relation":{},"subject":[],"published":{"date-parts":[[2024,10,6]]}}}