{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T08:00:04Z","timestamp":1773388804216,"version":"3.50.1"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T00:00:00Z","timestamp":1760227200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T00:00:00Z","timestamp":1760227200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,12]]},"DOI":"10.1109\/vlsi-soc64688.2025.11421770","type":"proceedings-article","created":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T20:31:18Z","timestamp":1773347478000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Exploring MRAM for On-Chip Texture Storage in Rendering Applications"],"prefix":"10.1109","author":[{"given":"Nicol\u00e1s","family":"Villegas","sequence":"first","affiliation":[{"name":"Universidad de los Andes,Santiago,Chile"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefano","family":"Romanini","sequence":"additional","affiliation":[{"name":"Universidad de los Andes,Santiago,Chile"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Moritz","family":"Scherer","sequence":"additional","affiliation":[{"name":"Mosaic SoC,Zurich,Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Warren","family":"Hunt","sequence":"additional","affiliation":[{"name":"Meta Reality Labs Menlo Park,California,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Syed Shakib","family":"Sarwar","sequence":"additional","affiliation":[{"name":"Meta Reality Labs Menlo Park,California,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Barbara De","family":"Salvo","sequence":"additional","affiliation":[{"name":"Meta Reality Labs Menlo Park,California,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chiao","family":"Liu","sequence":"additional","affiliation":[{"name":"Meta Reality Labs Menlo Park,California,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francesco","family":"Conti","sequence":"additional","affiliation":[{"name":"University of Bologna,Bologna,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Rossi","sequence":"additional","affiliation":[{"name":"University of Bologna,Bologna,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"University of Bologna,Bologna,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jorge","family":"G\u00f3mez","sequence":"additional","affiliation":[{"name":"Universidad de los Andes,Santiago,Chile"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC59245.2023.00022"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3385987"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC59616.2023.10268718"},{"key":"ref8","first-page":"1","article-title":"Reliability and magnetic immunity of reflow-capable embedded stt-mram in 16nm finfet cmos process","volume-title":"2021 Symposium on VLSI Technology","author":"Chen"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067837"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-27776-7_34"},{"key":"ref11","article-title":"Method and system for tile binning using half-plane edge function","volume-title":"Patent","author":"Min","year":"2013"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s00371-016-1241-0"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/RT.2007.4342588"}],"event":{"name":"2025 IFIP\/IEEE 33rd International Conference on Very Large Scale Integration (VLSI-SoC)","location":"Puerto Varas, Chile","start":{"date-parts":[[2025,10,12]]},"end":{"date-parts":[[2025,10,15]]}},"container-title":["2025 IFIP\/IEEE 33rd International Conference on Very Large Scale Integration (VLSI-SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11421694\/11421707\/11421770.pdf?arnumber=11421770","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T05:04:38Z","timestamp":1773378278000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11421770\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,12]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/vlsi-soc64688.2025.11421770","relation":{},"subject":[],"published":{"date-parts":[[2025,10,12]]}}}