{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:43:22Z","timestamp":1730303002384,"version":"3.28.0"},"reference-count":4,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1109\/vlsic.2012.6243814","type":"proceedings-article","created":{"date-parts":[[2012,7,31]],"date-time":"2012-07-31T16:37:23Z","timestamp":1343752643000},"page":"110-111","source":"Crossref","is-referenced-by-count":0,"title":["Isolated Preset Architecture for a 32nm SOI embedded DRAM macro"],"prefix":"10.1109","author":[{"given":"John","family":"Barth","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Don","family":"Plass","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adis","family":"Vehabovic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajiv","family":"Joshi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rouwaida","family":"Kanj","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steve","family":"Burns","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Todd","family":"Weaver","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"A 0.039 ? m2 High Performance eDRAM Cell based on 32nm High-K\/Metal SOI Technology","author":"butt","year":"0","journal-title":"2010 IEDM Dig Tech Papers"},{"key":"2","first-page":"70","article-title":"A 5.2GHz Microprocessor Chip for the IBM zEnterpriseTM System","volume":"54","author":"warnock","year":"2011","journal-title":"ISSCC"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/ISSCC.2010.5433814"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/ISSCC.2004.1332665"}],"event":{"name":"2012 IEEE Symposium on VLSI Circuits","start":{"date-parts":[[2012,6,13]]},"location":"Honolulu, HI, USA","end":{"date-parts":[[2012,6,15]]}},"container-title":["2012 Symposium on VLSI Circuits (VLSIC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6235082\/6243757\/06243814.pdf?arnumber=6243814","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T19:24:18Z","timestamp":1490124258000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6243814\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/vlsic.2012.6243814","relation":{},"subject":[],"published":{"date-parts":[[2012,6]]}}}