{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T23:49:49Z","timestamp":1725666589906},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/vlsic.2014.6858395","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T17:17:15Z","timestamp":1406654235000},"page":"1-2","source":"Crossref","is-referenced-by-count":3,"title":["A 75dB DR 50MHz BW 3&lt;sup&gt;rd&lt;\/sup&gt; order CT-&amp;#x0394;&amp;#x03A3; modulator using VCO-based integrators"],"prefix":"10.1109","author":[{"given":"Brian","family":"Young","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karthik","family":"Reddy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sachin","family":"Rao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amr","family":"Elshazly","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tejasvi","family":"Anand","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pavan Kumar","family":"Hanumolu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation","author":"rao","year":"2011","journal-title":"VLSIC"},{"key":"2","article-title":"A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS","author":"rao","year":"2013","journal-title":"VLSIC"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243842"},{"key":"7","article-title":"A 4GHz continuous-time ADC with 70dB DR and-74dBFS THD in 125MHz BW","author":"bolatkale","year":"2011","journal-title":"ISSCC"},{"key":"6","article-title":"A 0.13?m CMOS 78dB SNDR 87mW 20MHz BW CT ADC with VCO-based integrator and quantizer","author":"park","year":"2009","journal-title":"ISSCC"},{"key":"5","article-title":"A 10-bit 20MHz 38mW 950MHz CT ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13MOS","author":"straayer","year":"2007","journal-title":"VLSIC"},{"key":"4","article-title":"A 16mW 78dB-SNDR 10MHz-BW CT-ADC using residue-cancelling VCO-based quantizer","author":"reddy","year":"2012","journal-title":"ISSCC"}],"event":{"name":"2014 IEEE Symposium on VLSI Circuits","start":{"date-parts":[[2014,6,10]]},"location":"Honolulu, HI, USA","end":{"date-parts":[[2014,6,13]]}},"container-title":["2014 Symposium on VLSI Circuits Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6850260\/6858353\/06858395.pdf?arnumber=6858395","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T15:34:54Z","timestamp":1490283294000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6858395\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/vlsic.2014.6858395","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}