{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T10:27:02Z","timestamp":1768818422262,"version":"3.49.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/vlsic.2018.8502404","type":"proceedings-article","created":{"date-parts":[[2018,11,16]],"date-time":"2018-11-16T03:04:38Z","timestamp":1542337478000},"page":"33-34","source":"Crossref","is-referenced-by-count":103,"title":["Sticker: A 0.41-62.1 TOPS\/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers"],"prefix":"10.1109","author":[{"given":"Zhe","family":"Yuan","sequence":"first","affiliation":[]},{"given":"Jinshan","family":"Yue","sequence":"additional","affiliation":[]},{"given":"Huanrui","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Zhibo","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Jinyang","family":"Li","sequence":"additional","affiliation":[]},{"given":"Yixiong","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Qingwei","family":"Guo","sequence":"additional","affiliation":[]},{"given":"Xueqing","family":"Li","sequence":"additional","affiliation":[]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Yongpan","family":"Liu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","author":"zhang","year":"2016","journal-title":"ISCA"},{"key":"ref3","author":"han","year":"2016","journal-title":"ISCA"},{"key":"ref10","author":"qiu","year":"2016","journal-title":"FPGA"},{"key":"ref6","author":"parashar","year":"2017","journal-title":"ISCA"},{"key":"ref5","author":"albericio","year":"2016","journal-title":"ISCA"},{"key":"ref8","author":"moons","year":"2016","journal-title":"VLSI"},{"key":"ref7","author":"chen","year":"2016","journal-title":"ISSCC"},{"key":"ref2","author":"han","year":"2016","journal-title":"NIPS"},{"key":"ref9","author":"moons","year":"2017","journal-title":"ISSCC"},{"key":"ref1","author":"sim","year":"2016","journal-title":"ISSCC"}],"event":{"name":"2018 IEEE Symposium on VLSI Circuits","location":"Honolulu, HI","start":{"date-parts":[[2018,6,18]]},"end":{"date-parts":[[2018,6,22]]}},"container-title":["2018 IEEE Symposium on VLSI Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8484863\/8502213\/08502404.pdf?arnumber=8502404","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T00:17:26Z","timestamp":1598228246000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8502404\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/vlsic.2018.8502404","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}