{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:33:56Z","timestamp":1767339236272,"version":"3.41.2"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,6]]},"DOI":"10.1109\/vlsicircuits18222.2020.9162828","type":"proceedings-article","created":{"date-parts":[[2020,8,10]],"date-time":"2020-08-10T18:28:11Z","timestamp":1597084091000},"page":"1-2","source":"Crossref","is-referenced-by-count":3,"title":["A Fast Locking 5.8 \u2013 7.2 GHz Fractional-N Synthesizer with Sub-2 us Settling Time in 22 nm FDSOI"],"prefix":"10.1109","author":[{"given":"Jeffrey","family":"Prinzie","sequence":"first","affiliation":[{"name":"KU Leuven, Belgium"}]},{"given":"Shuja","family":"Andrabi","sequence":"additional","affiliation":[{"name":"MediaTek, UK"}]},{"given":"Christophe","family":"Beghein","sequence":"additional","affiliation":[{"name":"MediaTek, UK"}]},{"given":"Changhua","family":"Cao","sequence":"additional","affiliation":[{"name":"MediaTek, TX, US"}]},{"given":"Xiaochuan","family":"Guo","sequence":"additional","affiliation":[{"name":"MediaTek, TX, US"}]},{"given":"Jon","family":"Strange","sequence":"additional","affiliation":[{"name":"MediaTek, UK"}]},{"given":"Bernard","family":"Tenbroek","sequence":"additional","affiliation":[{"name":"MediaTek, UK"}]}],"member":"263","reference":[{"key":"ref4","first-page":"3540","author":"liu","year":"2018","journal-title":"JSSCC"},{"key":"ref3","first-page":"172","author":"chillara","year":"2014","journal-title":"ISSCC Dig Tech Paper"},{"journal-title":"Trans VLSI","year":"2019","author":"paliwal","key":"ref6"},{"key":"ref5","first-page":"3446","author":"yao","year":"2017","journal-title":"JSSCC"},{"key":"ref2","first-page":"350","author":"tang","year":"2019","journal-title":"ISSCC Dig Tech Paper"},{"key":"ref1","first-page":"181","author":"staszewski","year":"2007","journal-title":"TCASII"}],"event":{"name":"2020 IEEE Symposium on VLSI Circuits","start":{"date-parts":[[2020,6,16]]},"location":"Honolulu, HI, USA","end":{"date-parts":[[2020,6,19]]}},"container-title":["2020 IEEE Symposium on VLSI Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9146894\/9162771\/09162828.pdf?arnumber=9162828","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,28]],"date-time":"2025-07-28T19:46:00Z","timestamp":1753731960000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9162828\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,6]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/vlsicircuits18222.2020.9162828","relation":{},"subject":[],"published":{"date-parts":[[2020,6]]}}}