{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T20:20:46Z","timestamp":1774383646740,"version":"3.50.1"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,6]]},"DOI":"10.1109\/vlsicircuits18222.2020.9162949","type":"proceedings-article","created":{"date-parts":[[2020,8,10]],"date-time":"2020-08-10T18:28:11Z","timestamp":1597084091000},"page":"1-2","source":"Crossref","is-referenced-by-count":19,"title":["A 617 TOPS\/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS"],"prefix":"10.1109","author":[{"given":"Phil C.","family":"Knag","sequence":"first","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gregory K.","family":"Chen","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H. Ekin","family":"Sumbul","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raghavan","family":"Kumar","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark A.","family":"Anders","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Himanshu","family":"Kaul","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven K.","family":"Hsu","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amit","family":"Agarwal","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Monodeep","family":"Kar","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seongjong","family":"Kim","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ram K.","family":"Krishnamurthy","sequence":"additional","affiliation":[{"name":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","author":"yue","year":"2019","journal-title":"ISSCC"},{"key":"ref3","author":"bankman","year":"2019","journal-title":"JSSC"},{"key":"ref6","author":"auth","year":"2017","journal-title":"IEDM"},{"key":"ref5","author":"moons","year":"2018","journal-title":"CICC"},{"key":"ref2","author":"valavi","year":"2019","journal-title":"JSSC"},{"key":"ref1","author":"hubara","year":"2016","journal-title":"NIPS"}],"event":{"name":"2020 IEEE Symposium on VLSI Circuits","location":"Honolulu, HI, USA","start":{"date-parts":[[2020,6,16]]},"end":{"date-parts":[[2020,6,19]]}},"container-title":["2020 IEEE Symposium on VLSI Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9146894\/9162771\/09162949.pdf?arnumber=9162949","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,28]],"date-time":"2025-07-28T19:45:59Z","timestamp":1753731959000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9162949\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,6]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/vlsicircuits18222.2020.9162949","relation":{},"subject":[],"published":{"date-parts":[[2020,6]]}}}