{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T06:37:43Z","timestamp":1773815863474,"version":"3.50.1"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,1,3]],"date-time":"2026-01-03T00:00:00Z","timestamp":1767398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,3]],"date-time":"2026-01-03T00:00:00Z","timestamp":1767398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,1,3]]},"DOI":"10.1109\/vlsid68508.2026.00016","type":"proceedings-article","created":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:19:04Z","timestamp":1773778744000},"page":"7-12","source":"Crossref","is-referenced-by-count":0,"title":["An FPGA-Based Secure and Privacy-Aware RISC-V SoC with a CNN Accelerator for Edge AI"],"prefix":"10.1109","author":[{"given":"Priyanshu","family":"Tyagi","sequence":"first","affiliation":[{"name":"IIT Roorkee"}]},{"given":"Rhythm","family":"Patel","sequence":"additional","affiliation":[{"name":"SVNIT Surat"}]},{"given":"Sparsh","family":"Mittal","sequence":"additional","affiliation":[{"name":"IIT Roorkee"}]},{"given":"Rekha","family":"Singhal","sequence":"additional","affiliation":[{"name":"TCS Research"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-44534-8_15"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062207"},{"key":"ref3","author":"Assir","year":"2021","journal-title":"Arrow: A risc-v vector accelerator for machine learning inference"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/1631\/1\/012002"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3570928"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530439"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.14711\/thesis-991012879963103412"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586199"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530439"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1098\/rsta.2019.0155"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3179227"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.2478\/popets-2020-0028"}],"event":{"name":"2026 39th International Conference on VLSI Design &amp; 25th International Conference on Embedded Systems (VLSID)","location":"Pune, India","start":{"date-parts":[[2026,1,3]]},"end":{"date-parts":[[2026,1,7]]}},"container-title":["2026 39th International Conference on VLSI Design &amp;amp; 25th International Conference on Embedded Systems (VLSID)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11433189\/11433171\/11433266.pdf?arnumber=11433266","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T05:40:37Z","timestamp":1773812437000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11433266\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,3]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/vlsid68508.2026.00016","relation":{},"subject":[],"published":{"date-parts":[[2026,1,3]]}}}