{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T06:21:35Z","timestamp":1773814895048,"version":"3.50.1"},"reference-count":30,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,1,3]],"date-time":"2026-01-03T00:00:00Z","timestamp":1767398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,3]],"date-time":"2026-01-03T00:00:00Z","timestamp":1767398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,1,3]]},"DOI":"10.1109\/vlsid68508.2026.00064","type":"proceedings-article","created":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:19:04Z","timestamp":1773778744000},"page":"293-298","source":"Crossref","is-referenced-by-count":0,"title":["Security-aware Performance-Optimized Computation Offloading Under Near Memory Processing"],"prefix":"10.1109","author":[{"given":"Simran Preet","family":"Kaur","sequence":"first","affiliation":[{"name":"Indian Institute of Information Technology Guwahati,Department of Computer Science and Engineering,Assam,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Asutosh Kumar","family":"Sarma","sequence":"additional","affiliation":[{"name":"Indian Institute of Information Technology Guwahati,Department of Computer Science and Engineering,Assam,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satanu","family":"Maity","sequence":"additional","affiliation":[{"name":"Indian Institute of Information Technology Guwahati,Department of Computer Science and Engineering,Assam,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manojit","family":"Ghose","sequence":"additional","affiliation":[{"name":"Indian Institute of Information Technology Guwahati,Department of Computer Science and Engineering,Assam,India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.98"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/WICT.2012.6409239"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC-SmartCity-DSS.2017.23"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SEED55351.2022.00023"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2022.3196499"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-77360-3_7"},{"key":"ref7","first-page":"719","article-title":"FLUSH+RELOAD: A high resolution, low noise, L3 cache side-channel attack","volume-title":"23rd USENIX Security Symposium","author":"Yarom","year":"2014"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3567917"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3386901.3388888"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-017-0025-y"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00037"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3497776.3517778"},{"key":"ref13","article-title":"Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory","volume-title":"26th USENIX Security Symposium","author":"Gruss","year":"2017"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2976749.2978360"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527431"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2025.3542361"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2022.3226132"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.43"},{"key":"ref20","author":"Page","year":"2005","journal-title":"Partitioned Cache Architecture as a Side-Channel Defence Mechanism"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HOST55118.2023.10133713"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898086"},{"key":"ref23","author":"Brickell","year":"2006","journal-title":"Software mitigations to hedge AES against cache-based software side channel vulnerabilities"},{"key":"ref24","article-title":"Cipherfix: Mitigating ciphertext Side-Channel attacks in software","volume-title":"32nd USENIX Security Symposium","author":"Wichelmann","year":"2023"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCC.2014.2358236"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/tetc.2024.3495218"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TrustCom56396.2022.00042"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.23919\/date58400.2024.10546698"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"}],"event":{"name":"2026 39th International Conference on VLSI Design &amp; 25th International Conference on Embedded Systems (VLSID)","location":"Pune, India","start":{"date-parts":[[2026,1,3]]},"end":{"date-parts":[[2026,1,7]]}},"container-title":["2026 39th International Conference on VLSI Design &amp;amp; 25th International Conference on Embedded Systems (VLSID)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11433189\/11433171\/11433309.pdf?arnumber=11433309","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T05:28:29Z","timestamp":1773811709000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11433309\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,3]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/vlsid68508.2026.00064","relation":{},"subject":[],"published":{"date-parts":[[2026,1,3]]}}}